Nonvolatile memory system, semiconductor memory and writing method

• US 5,982,668 A
• Filed: 08/18/1998
• Issued: 11/09/1999
• Est. Priority Date: 07/09/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Engineering Corp
• Inventors: Ishii, Tatsuya, Tsuchiya, Osamu, Miwa, Hitoshi, Kubono, Shooji
• Primary Examiner(s): Phan, Trong
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US09/135,175
• Time in Patent Office: 448 Days
• Field of Search: 365/185.24, 365/185.22, 365/185.18, 365/185.21, 365/185.29
• US Class Current: 365/185.24
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

Claims

1. A nonvolatile semiconductor memory device formed on a single semiconductor chip, comprising:

a plurality of memory cells each of which includes one transistor and which stores information as a threshold voltage;

a plurality of word lines each of which is coupled with corresponding memory cells of said plurality of memory cells;

a terminal; and

a controller which controls an operation for putting a threshold voltage of each memory cell coupled to a selected one of said plurality of word lines to one of an erased state and a written state, in response to a command supplied to said terminal,

wherein in response to said command, said controller controls the threshold voltage of said memory cells coupled to said selected word line so as to collectively move the threshold voltage of said memory cells coupled to said selected word line to a predetermined direction, and controls a writing operation with respect to a memory cell put to said written state before said command is supplied to said terminal and with respect to at least one of said memory cells coupled to said selected word line.

2. The nonvolatile semiconductor memory device according to claim 1, further comprising a data register in which write expected value data is stored for said memory cells coupled to said selected word line based on data read from said memory cells coupled to said selected word line and data to be written to said at least one memory cell after said command is supplied to said terminal.

3. The nonvolatile semiconductor memory device according to claim 2, wherein said data to be written is supplied to said data register from said terminal.

4. The nonvolatile semiconductor memory device according to claim 3, further comprising a plurality of data lines each of which is coupled with corresponding memory cells of said plurality of memory cells, wherein said data register is coupled to each of said plurality of data lines and stores data of said memory cells coupled to said selected word line.

5. The nonvolatile semiconductor memory device according to claim 4, further comprising a data inverting circuit which is coupled to each of said plurality of data lines and which forms said write expected value data from said data read from said memory cells coupled to said selected word line and said data to be written from said terminal.

6. The nonvolatile semiconductor memory device according to claim 5, wherein said threshold voltage exists within a voltage range having a first region indicating said erased state and a second region indicating said written state.

7. The nonvolatile semiconductor memory device according to claim 6, wherein said predetermined direction is toward said first region from said first region.

8. The nonvolatile semiconductor memory device according to claim 7, wherein said plurality of memory cells are in an erased state when the, threshold voltage of said plurality of memory cells is placed in said first region and said plurality of memory cells are in a written state when the threshold voltage is placed in said second region;

and wherein the threshold voltage of a memory cell in said written state and coupled to said selected word line is moved between said first and second regions by execution of said command.

9. The nonvolatile semiconductor memory device according to claim 7, wherein said plurality of memory cells are in an erased state when the threshold voltage of said ma plurality of memory cells is placed in said first region and said plurality of memory cells are in a written state when the threshold voltage is placed in said second region;

and wherein the threshold voltage of said memory cells coupled to said selected word line is moved to said first region by execution of said command.

10. A nonvolatile semiconductor memory device formed on a single semiconductor chip, comprising:

a plurality of memory cells each of which is a single transistor and which stores data corresponding to one of a written state and an erased state as a threshold voltage;

a terminal;

a data register; and

a controller controlling a threshold voltage of a memory cell in accordance with a command supplied from said terminal,

wherein when a command indicating an additional write operation is supplied from said terminal, said controller controls synthesized data of data read from selected memory cells of said plurality of memory cells and data supplied from said terminal to be stored in said data register, and controls said selected memory cells to be written in accordance with said synthesized data stored in said data register after the threshold voltage of said selected memory cells is moved toward said erased state.

11. The nonvolatile semiconductor memory device according to claim 10, further comprising a plurality of data lines, wherein each of said plurality of data lines is coupled with corresponding memory cells and said data register.

12. The nonvolatile semiconductor memory device according to claim 11, further comprising a rewriting circuit, wherein said rewriting circuit is coupled to said plurality of data lines and forms said synthesized data from said read data and said supplied data from said terminal.

13. The nonvolatile semiconductor memory device according to claim 12, further comprising a plurality of word lines each of which is coupled with corresponding memory cells of said plurality of memory cells.

14. The nonvolatile semiconductor memory device according to claim 13, further comprising a decoder decoding address signals and selecting a word line from said plurality of word lines.

15. The nonvolatile semiconductor memory device according to claim 14, wherein said address signals are supplied from said terminal.

16. A nonvolatile semiconductor memory device formed on a single semiconductor chip, comprising:

a plurality of memory cells each of which is a single transistor and which stores data corresponding to one of a written state and an erased state as a threshold voltage;

a terminal;

a sense latch circuit storing data supplied from said terminal and data read from selected memory cells;

a controller controlling a threshold voltage of a memory cell in accordance with a command supplied from said terminal; and

a voltage source circuit generating an erase voltage under control by said controller;

wherein when a command indicating an additional write operation is supplied from said terminal, synthesized data of data read from selected memory cells of said plurality of memory cells and data supplied from said terminal are stored in said sense latch circuits, and said selected memory cells are written in accordance with said synthesized data stored in said sense latch circuits after said selected memory cells are supplied with said erase voltage in a predetermined time under control by said controller.

17. The nonvolatile semiconductor memory device according to claim 16, further comprising a plurality of data lines, wherein each of said plurality of data lines is coupled with corresponding memory cells and said sense latch circuits.

18. The nonvolatile semiconductor memory device according to claim 17, further comprising a rewriting circuit, wherein said rewriting circuit is coupled to said plurality of data lines and forms said synthesized data from said read data and said supplied data from said terminal.

19. The nonvolatile semiconductor memory device according to claim 18, further comprising a plurality of word lines each of which is coupled with corresponding memory cells of said plurality of memory cells.

20. The nonvolatile semiconductor memory device according to claim 19, further comprising a decoder decoding address signals and selecting a word line from said plurality of word lines.

21. The nonvolatile semiconductor memory device according to claim 20, wherein said address signals are supplied from said terminal.

22. The nonvolatile semiconductor memory device according to claim 21, wherein the time during which said erase voltage is being supplied to said selected memory cells by said command indicating said additional write operation is shorter than the time during which said erase voltage is being supplied to selected memory cells by a command indicating an erase operation.