EDRAM having a dynamically-sized cache memory and associated method

• US 5,983,313 A
• Filed: 04/10/1996
• Issued: 11/09/1999
• Est. Priority Date: 04/10/1996
• Status: Expired due to Fees

• Current Assignee: Ramtron International Corporation (Infineon Technologies AG)
• Original Assignee: Ramtron International Corporation (Infineon Technologies AG)
• Inventors: Heisler, Dion Nickolas, Heisler, Doyle James, Joseph, James Dean
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US08/630,489
• Time in Patent Office: 1,308 Days
• Field of Search: 364/DIG. 1, 364/243.4, 711/105, 711/136, 711/160, 711/118, 711/134, 711/3, 711/119, 365/189.05
• US Class Current: 711/105
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value

Abstract

The method and apparatus of the current invention relates to an intelligent cache management system for servicing a main memory and a cache. The cache resources are allocated to segments of main memory rows based on a simple or complex allocation process. The complex allocation performs a predictive function allocating scarce resources based on the probability of future use. The apparatus comprises a main memory coupled by a steering unit to a cache. The steering unit controls where in cache a given main memory row segment will be placed. The operation of the steering unit is controlled by an intelligent cache allocation unit. The unit allocates new memory access requests cache locations which are least frequently utilized. Since a given row segment may be placed anywhere in a cache row, the allocation unit performs the additional function of adjusting the column portion of a memory access request to compensate for the placement of the requested segment in the cache. The allocation unit accepts as input hit or miss information from page segment comparators greater than or equal to in number the number of segments of cache.

Claims

1. Memory apparatus for storing data, the data accessible responsive to a memory access request, tho memory access request identifying data by row and column, said memory apparatus comprising:

a main memory formed of an array of memory elements, the array formed of rows and columns of memory elements;

a cache memory selectably formed of at least one cache segment, the at least one cache segment capable of storing uploaded data uploaded from row segment portions of rows of memory elements of said main memory, data stored in a row of said cache memory selectably of data uploaded from more than one row of said main memory;

at least one comparator coupled to receive indications of the memory access request, said comparator for determining whether data identified in the memory access request is stored in said cache memory;

an allocator operable at least responsive to determinations made by said comparator, said allocator for identifying locations of the at least one cache segment of said cache memory corresponding to the data identified by row and column in the memory access request when said comparator determines the data to be stored in said cache memory, said allocator having a first location register and a second location register which contain information to indicate in which portion of the cache memory that the data resides, a two-input logical exclusive-or gate having a first input coupled to said fixed location register and a second input coupled to said second location register, and to a column adjust register, said two-input logical exclusive-or gate for getting the information contained in said first and second location registers, respectively, to said column adjust register, said column adjust register containing thereby an adjustment value, the adjustment value for allocating portions of the at least one cache segment to be overwritten with data retrieved from said main memory corresponding to the row and column identified in the memory access request when said comparator determines the data not to be store in said cache memory, allocation of the portions of the cache segment to which the data is to be overwritten selected responsive to frequency of utilization of the cache segment, said locator further for steering of the data uploaded from said main memory to said cache memory subsequent to the determination by said comparator that the data is stored in said cache memory.

2. The memory apparatus of claim 1 wherein said comparator determines both which row and which cache segment of the at least one cache segment the data identified in the memory access request and determined to be in said cache memory is located.

3. The memory apparatus of claim 1 wherein said comparator comprises a latch device for latching signal contents representative of locations at which the data identified by the memory access request are to be uploaded from said main memory to said cache memory.

4. The memory apparatus of claim 1 wherein said at least one comparator at least correspond in number with a number of cache segments of which said cache memory is selectably formed.

5. A method for accessing data stored in a memory apparatus responsive to a memory access request which identifies the data requested to be accessed by row and column, said method comprising the steps of:

providing a main memory formed of an array of memory elements, the array formed of rows and columns of memory elements;

selectably uploading data retrieved from row segment portions of rows of memory elements of the main memory provided during said step of providing to be stored in a cache memory, the data uploaded and stored in a row of the cache memory selectably retrieved from more than one row of the main memory;

determining, responsive to the memory access request, whether the data identified in the data access request is stored in the cache memory during said step of selectably uploading;

identifying locations of the cache memory corresponding to the data identified by row and column in the memory access request when a determination is made during said step of determining that the data identified in the memory access request is stored in the cache memory;

allocating portions of the cache memory to be overwritten with data to be retrieved from the main memory corresponding to the row and column identified in the memory access request when a determination is made during said step of determining that the data identified in the memory access request is not stored in the cache memory, the portions of the cache memory selected to be overwritten by providing first and second location register containing information to indicate which portion of the cache memory that the data resides, providing the information contained at the first location register to a first input of a two-input logical exclusive- or gate, providing the information contained at the second location register to a second input of the two-input logical exclusive-or gate, gating the information provided to the two-input logical exclusive-or gate to a column adjust register to form an adjustment value thereat, the adjustment value for allocating the portions of the cache memory to be overwritten with the data, the portions of the cache memory allocated to be overwritten selected responsive to frequency of utilization of the cache segment; and

steering the data uploaded from the main memory to the cache memory subsequent to a determination during said operation of determining that the data is not stored in the cache memory.

6. The method of claim 5 further comprising the additional step, prior to said step of steering, of retrieving the data identified in the memory access request from the memory elements of the main memory, and wherein said step of steering comprises the steps of uploading the data retrieved during said step of retrieving to the cache memory, and overwriting the portions of the cache memory allocated during said step of allocating with the data retrieve during said step of retrieving.

7. The method of claim 5 wherein the cache memory is divided into a first cache segment and at least a second cache segment and wherein the locations of the cache memory identified during said step of identifying identify both which row and which of the first and at least second cache segment, respectively, in which the data identified in the memory access request is stored.