Method and apparatus for externally configuring and modifying the transaction request response characteristics of a semiconductor device coupled to a bus

• US 5,983,320 A
• Filed: 08/13/1997
• Issued: 11/09/1999
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): SHIN, CHRISTOPHER B
• Application Number:
  US08/910,810
• Time in Patent Office: 818 Days
• Field of Search: 395/325, 395/200, 395/275, 395/700, 395/800, 395/892, 395/871, 395/427, 395/411, 395/410, 395/810, 711/114, 711/100, 711/81
• US Class Current: 711/114
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system having a bus, a bus master, and a plurality of semiconductor devices having bus transaction response characteristics that are configurable by the bus master via the bus. Each semiconductor device includes at least one register that is operative to store information specifying a manner in which the semiconductor device is to respond to transaction requests received from the bus. The bus master transmits the information to the semiconductor device via the bus lines of the bus when the bus in configured. The semiconductor device stores the information received from the bus lines in the register during configuration of the bus and thereafter responds to requests according to the information stored in register. Configurable bus transaction response characteristics may include a unique device identification for the semiconductor device, a range of addresses to which the semiconductor corresponds, or the bus access-time of the semiconductor device. The semiconductor device may be a memory device.

Claims

1. A memory subsystem comprising:

a bus comprising a group of general purpose signal lines carrying substantially all time-division multiplexed address, data, and control information for a memory transaction; and

a memory device coupled to the bus, the memory device receiving and decoding the time-division multiplexed address, data, and control information, the control information indicating the memory transaction to be performed by the memory device, the memory device comprising individually addressable discrete memory sections and address registers each for storing information indicative of a range of addresses for a corresponding one of the individually addressable discrete memory sections, the memory device performing the memory transaction indicated by the control information if the address information specifies an address within one of the corresponding range of addresses.

2. The computer system of claim 1, wherein the memory device is a dynamic random access memory.

3. The computer system of claim 1 wherein each of the individually addressable discrete memory sections comprises an array of memory cells.

8. The memory subsystem of claim 1, wherein the individually addressable discrete memory sections comprise:

a plurality of operational individually addressable discrete memory sections; and

and at least one non-operational individually addressable discrete memory section, wherein information stored in each of the address registers corresponding to the plurality of operational individually addressable discrete memory sections collectively indicates a contiguous range of addresses in the memory device excluding the at least one non-operational individually addressable discrete memory section.

9. The memory subsystem of claim 1, further comprising:

a bus master coupled to the bus, the bus master transmitting the time-division multiplexed address, data, and control information to the memory device via the bus.

11. The memory subsystem of claim 1, wherein the memory device comprises a plurality of memory devices each comprising individually addressable discrete memory sections and address registers for storing information indicative of a range of addresses for a corresponding one of the individually addressable discrete memory sections, wherein:

one of the individually addressable discrete memory sections in one of the memory devices is non-operational; and

the information stored in each of the other individually addressable discrete memory sections collectively indicates a contiguous range of addresses in the memory devices excluding the non-operational individually addressable discrete memory section.

4. A memory device that is programmable to respond to a range of addresses, comprising:

at least one pin for coupling the memory device to a bus in a memory subsystem, the bus comprising a group of general purpose signal lines carrying substantially all time-division multiplexed address, data, and control information for a memory transaction, the control information indicating the memory transaction to be performed by the memory device;

at least one addressable discrete memory section; and

at least one programmable address register for storing information indicative of the range of addresses for the at least one addressable discrete memory section, the memory device performing the memory transaction indicated by the control information if the address information specifies an address within one of the range of addresses.

5. The memory device of claim 4, wherein the memory device is a dynamic random access memory.

6. The memory device of claim 4 wherein the at least one addressable discrete memory section comprises an array of memory cells.

7. A method for programming a memory device to respond to a range of addresses, the memory device having individually addressable discrete memory sections, the method comprising the steps of:

the memory device receiving time-division multiplexed address, data and control information from a bus, the bus comprising a group of general purpose signal lines carrying substantially all of the time-division multiplexed address, data, and control information for a memory transaction, wherein the address information is indicative of a range of addresses for a corresponding one of the individually addressable discrete memory sections of the memory device;

decoding the time-division multiplexed address, data, and control information;

writing the address information to address registers of the memory device according to the decoded control information; and

the memory device thereafter responding to memory transaction requests indicated by the control information when the address information specifies an address within one of the corresponding range of addresses.

10. The method of claim 7, wherein the memory device is a dynamic random access memory device (DRAM).

12. A memory subsystem comprising:

a bus comprising a group of general purpose signal lines carrying substantially all time-division multiplexed address and control information for a memory transaction; and

a memory device coupled to the bus, the memory device receiving and decoding the time-division multiplexed address and control information, the control information indicating a transaction to be performed by the memory device, the memory device comprising at least one addressable discrete memory section and at least one address register storing information indicative of the range of addresses for the at least one addressable discrete memory section, the memory device performing the memory transaction indicated by the control information if the address information specifies an address within one of the range of addresses.

13. The memory subsystem of claim 12, wherein the general purpose signal lines further carry data that is time-multiplexed with the address and control information.