Computer system having organization for multiple condition code setting and for testing instruction out-of-order
First Claim
1. A computer system comprising:
- multiple functional units for executing instructions;
issuing means for issuing instructions for processing by said functional units and including an instruction issue unit;
a buffer;
one or more register files;
a cache store coupled between main memory and said functional units;
an interconnection network coupling said functional units, said register files, and said instruction issue unit;
means for concurrently executing multiple out-of-order instructions;
means for attaching an I-Group comprising an instruction and a tag, a read-vector, a write vector, and a type vector as control bits for instructional use by the system for permitting the hardware of the system to schedule concurrently and on a short cycle time basis multiple, possibly out-of-order, instruction issuances to multiple functional units for execution and to transfer I-Groups to the buffer or for scheduling by said issue unit;
an instruction scheduling mechanism and in which the issue unit includes assigning means for concurrently assigning and issuing independent, multiple, out-of-order instructions contained in the instruction scheduling mechanism provided by said issue unit to the multiple functional units for execution; and
ports connecting the issue unit to the multiple functional units,wherein said assigning means includes prioritization means for prioritizing eligible instructions by the assignment to each port of a port-type through which an instruction of a matching instruction type, as specified in its I-Group, may be issued to a functional unit that is able to execute it so that independent instructions eligible for transfer may outnumber available functional units for paths via a port through which instructions may be transferred.
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Accused Products
Abstract
Computer system with multiple, out-of-order, instruction issuing system suitable for superscalar processors with a RISC organization, also has a Fast Dispatch Stack (FDS), a dynamic instruction scheduling system that may issue multiple, out-of-order, instructions each cycle to functional units as dependencies allow. The basic issuing mechanism supports a short cycle time and its capabilities are augmented. Condition code dependent instructions issue in multiples and out-of-order. A fast register renaming scheme is presented. An instruction squashing technique enables fast precise interrupts and branch prediction. Instructions preceding and following one or more predicted conditional branch instructions may issue out-of-order and concurrently. The effects of executed instructions following an incorrectly predicted branch instruction or an instruction that causes a precise interrupt are undone in one machine cycle.
148 Citations
17 Claims
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1. A computer system comprising:
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multiple functional units for executing instructions; issuing means for issuing instructions for processing by said functional units and including an instruction issue unit; a buffer; one or more register files; a cache store coupled between main memory and said functional units; an interconnection network coupling said functional units, said register files, and said instruction issue unit; means for concurrently executing multiple out-of-order instructions; means for attaching an I-Group comprising an instruction and a tag, a read-vector, a write vector, and a type vector as control bits for instructional use by the system for permitting the hardware of the system to schedule concurrently and on a short cycle time basis multiple, possibly out-of-order, instruction issuances to multiple functional units for execution and to transfer I-Groups to the buffer or for scheduling by said issue unit; an instruction scheduling mechanism and in which the issue unit includes assigning means for concurrently assigning and issuing independent, multiple, out-of-order instructions contained in the instruction scheduling mechanism provided by said issue unit to the multiple functional units for execution; and ports connecting the issue unit to the multiple functional units, wherein said assigning means includes prioritization means for prioritizing eligible instructions by the assignment to each port of a port-type through which an instruction of a matching instruction type, as specified in its I-Group, may be issued to a functional unit that is able to execute it so that independent instructions eligible for transfer may outnumber available functional units for paths via a port through which instructions may be transferred. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computer system comprising:
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multiple functional units for executing instructions; issuing means including an issue unit for issuing instructions for processing by said functional units; one or more register files; a main memory store; a cache store coupled between main memory and said functional units; an interconnection network coupling said functional units, said 11 register files, and said instruction issue unit; means for currently executing multiple out-of-order instructions; and instruction scheduling means for concurrently assigning and transferring independent, multiple, out-of-order instructions to multiple functional units for execution and wherein the number of independent instructions eligible for transfer may outnumber available functional units or paths through which instructions may be transferred, and including, assigning means for prioritizing eligible instructions in hardware by the assignment to each port of a port-type through which an instruction of a matching instruction type, as specified in its I-Group, may be issued to a functional unit that is able to execute it. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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Specification