Weighted random pattern built-in self-test

• US 5,983,380 A
• Filed: 09/16/1997
• Issued: 11/09/1999
• Est. Priority Date: 09/16/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Pateras, Stephen V., Shushereba, John James, Motika, Franco
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/931,558
• Time in Patent Office: 784 Days
• Field of Search: 371/22.5, 371/22.31, 371/22.33, 371/22.6, 371/27.1, 371/27.2, 364/580, 364/581, 364/717, 324/765, 395/183.06, 714/30, 714/32, 714/705, 714/725, 714/726, 714/727, 714/728, 714/729, 714/733, 714/739, 714/761
• US Class Current: 714/733
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern

Abstract

An integrated circuit comprising logic circuits and self-test circuits for testing logic circuits including a pseudo random pattern generator for generating at least one pseudo random pattern and weighing circuit for weighing the pseudo random pattern. The weighting circuit and pseudo random pattern generator generate a plurality of weighted pseudo random patterns including at least one pair of a first weighted pseudo random pattern and a second weighted pseudo random pattern that is the complement of the first pattern. A weighting instruction selects one of the first or second pseudo random patterns for testing the logic circuits.

Claims

1. An integrated circuit, comprising logic circuits connected to a scan chain and self-test circuits for testing said logic circuits, said self-test circuits comprising:

a pseudo random pattern generator for generating at least one pseudo random pattern;

a weighting circuit for providing a weight to said pseudo random pattern; and

a selection circuit for providing said weighted pseudo random pattern to said scan chain for scanning said weighted pattern to said logic circuits.

2. An integrated circuit as recited in claim 1, wherein said weighting circuit comprises a weight generating circuit and a weight selecting circuit.

3. An integrated circuit as recited in claim 2, wherein said selection circuit comprises a multiplexor.

4. The integrated circuit, as recited in claim 1, wherein said weighting circuit includes means for receiving a weighting instruction from external to said integrated circuit.

5. The integrated circuit, as recited in claim 4, wherein said pseudo random pattern generator and said weighting circuit generate a plurality of weighted pseudo random patterns and wherein said weighting instruction from external to said integrated circuit selects one of said weighted pseudo random patterns for providing to said scan chain for testing said logic circuits.

6. The integrated circuit, as recited in claim 5, wherein said plurality of weighted random patterns include at least one pair of a first weighted pseudo random pattern and a second weighted pseudo random pattern, said second pattern being a complement of said first pattern.

7. The integrated circuit, as recited in claim 6, wherein said weighting instruction selects one of said first or second patterns for testing said logic circuits.

8. The integrated circuit, as recited in claim 4, wherein said weighting instruction is generated by a tester external to said integrated circuit.

9. The integrated circuit, as recited in claim 4, further comprising a memory or register array wherein at least a portion of said weighting instruction is stored in said memory array.

10. The integrated circuit, as recited in claim 9, wherein said weighting circuit and said pseudo random pattern generator generate a plurality of weighted pseudo random patterns including at least one pair of a first weighted pseudo random pattern and a second weighted pseudo random pattern, said second pattern being a complement of said first pattern.

11. The integrated circuit, as recited in claim 10, wherein said weighing instruction selects one of said first or second patterns for testing said logic circuits.

12. A method of testing an integrated circuit, comprising logic circuits connected to a scan chain and self-test circuits for testing said logic circuits, the method comprising:

a) generating a pseudo random pattern;

b) providing a weight to said pseudo random pattern; and

c) providing said weighted pseudo random pattern to the scan chain for scanning said weighted pattern to the logic circuits.

13. The method as recited in claim 12, wherein said steps of generating and providing a weight generate a plurality of weighted pseudo random patterns for testing the logic circuits.

14. The method as recited in claim 12, further comprising the step of selecting one of said plurality of weighted pseudo random patterns for testing the logic circuits.

15. The method as recited in claim 13, wherein said plurality of weighted pseudo random patterns includes at least one pair of a first weighted pseudo random pattern and a second weighted pseudo random pattern, said second patten being a complement of the first pattern.

16. The method as recited in claim 15, further comprising the step of selecting one of the first or second patterns for testing the logic circuits.

17. The method as recited in claim 12, wherein said step (b) of providing a weight comprises the step of receiving a weighting instruction from external to said integrated circuit.

18. The method as recited in claim 17, further comprising the step of storinig said weighting instruction in a memory or register array of the integrated circuit.

19. The method as recited in claim 12, wherein said steps of generating and providing a weight generate a plurality of weighted pseudo random patterns including at least one pair of a first weighted pseudo random pattern and a second weighted pseudo random pattern, said second pattern being a complement of said first pattern.

20. The method as recited in claim 12, wherein said steps of generating a pseudo random pattern and providing a weight to said pseudo random pattern are accomplished with a circuit located on the integrated circuit.