High density three-dimensional IC interconnection

• US 5,985,693 A
• Filed: 05/02/1997
• Issued: 11/16/1999
• Est. Priority Date: 09/30/1994
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn Joseph
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US08/850,749
• Time in Patent Office: 928 Days
• Field of Search: 438/128, 438/106, 438/107, 438/108, 438/109, 438/445
• US Class Current: 438/107
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Claims

1. A method of forming a stacked integrated circuit, comprising the steps of:

fabricating a first integrated circuit on a first substrate;

fabricating a second integrated circuit on a second substrate; and

bonding the first and second substrates to form interconnects between the first integrated circuit and the second integrated circuit;

wherein said bonding is thermal diffusion bonding of the first substrate to the second substrate to form a stacked IC structure, including bonding of interconnect areas and non-interconnect areas, wherein in the non-interconnect areas, bonding is thermal diffusion bonding of an inorganic material.

2. The method of claim 1, wherein the inorganic material has silicon as a substantial constituent.

3. The method of claim 2, wherein at least some of said interconnects are vertical interconnects.

4. The method of claim 3, comprising the step of further bonding the stacked IC structure and a further substrate.

5. The method of claim 4, wherein said further bonding is thermal diffusion bonding of the stacked IC structure and the further substrate to one another.

6. The method of claim 5, wherein said thermal diffusion bonding uses contact patterns forming extensions of the vertical interconnects.

7. The method of claim 1, comprising the step of further bonding the stacked IC structure and a further substrate.

8. The method of claim 7, wherein said further bonding is bonding of a singulated stacked IC structure and the further substrate.

9. The method of claim 7, wherein said further bonding is thermal diffusion metal bonding of a vertical interconnect contact pattern of a singulated stacked IC structure and the further substrate.

10. The method of claim 1, comprising the further steps of:

fabricating at least one additional integrated circuit on at least one additional substrate; and

bonding the at least one additional substrate to the stacked IC substrate and forming interconnects between integrated circuits, wherein at least some of the interconnects pass through a substrate.

11. The method of claim 10, further comprising the step of:

thinning substrates on which integrated circuits are formed to form thinned substrates, facilitating formation of said interconnects.

12. The method of claim 11, wherein at least some of said interconnects are vertical interconnects.

13. The method of claim 11, wherein said thinned substrates are thinned to less than 50 mm in thickness.

14. The method of claim 13, wherein mating contact patterns are formed on respective surfaces to be bonded together.

15. The method of claim 14, wherein said mating contact patterns are formed of metal.

16. The method of claim 7, comprising the further steps of:

bonding dielectric surfaces of said substrates; and

forming said vertical interconnects by;

forming a via through an upper substrate to a lower substrate; and

filling the via with metal to complete an interconnection to the upper substrate.

17. A method of forming a stacked integrated circuit, comprising the steps of:

forming on corresponding surfaces of multiple integrated circuit wafers complementary patterns of a material bondable using thermal diffusion bonding; and

bonding the wafers together by thermal diffusion bonding of the complementary patterns;

wherein bonding includes bonding of interconnect areas and non-interconnect areas, wherein in the non-interconnect areas, bonding is thermal diffusion bonding of an inorganic material.

18. The method of claim 17, wherein the inorganic material has silicon as a substantial constituent.

19. A method of forming a stacked integrated circuit, comprising the steps of:

fabricating a first integrated circuit on a first substrate;

fabricating a second integrated circuit on a second substrate; and

bonding the first and second substrates to form interconnects between the first integrated circuit and the second integrated circuit;

wherein said bonding is thermal diffusion bonding of the first substrate to the second substrate to form a stacked IC structure, including bonding of interconnect areas and non-interconnect areas, wherein materials that are thermal diffusion bonded are limited to materials compatible with standard semiconductor processes, including at least one of the following;

metal and a material having silicon as a substantial constituent.

20. A method of forming a stacked integrated circuit, comprising the steps of:

forming on corresponding surfaces of multiple integrated circuit wafers complementary patterns of a material bondable using thermal diffusion bonding; and

bonding the wafers together by thermal diffusion bonding of the complementary patterns;

wherein bonding includes bonding of interconnect areas and non-interconnect areas, wherein materials that are thermal diffusion bonded are limited to materials compatible with standard semiconductor processes, including at least one of the following;

metal and a material having silicon as a substantial constituent.