Method of manufacturing vertical power device

• US 5,985,708 A
• Filed: 03/13/1997
• Issued: 11/16/1999
• Est. Priority Date: 03/13/1996
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kurobe, Atsusi, Yamaguchi, Yoshihiro, Matsudai, Tomoko, Yasuhara, Norio, Funaki, Hideyuki, Kawaguchi, Yusuke, Nakagawa, Akio, Sugiyama, Naoharu
• Primary Examiner(s): Chaudhari, Chandra
• Application Number:
  US08/816,596
• Time in Patent Office: 978 Days
• Field of Search: 257/341, 257/350, 438/138, 438/206, 438/209, 438/212, 438/268
• US Class Current: 438/206
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7317 Bipolar thin film transistors
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 29/78639 with a drain or source connected to a bulk conducting substrate
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor apparatus comprising a vertical type semiconductor device having a first conducting type semiconductor substrate, a drain layer formed on the surface of the semiconductor substrate, a drain electrode formed on the surface of the drain layer, a second conducting type base layer selectively formed on the surface of the semiconductor substrate opposite to the drain layer, a first conducting type source layer selectively formed on the surface of the second conducting type base layer, a source electrode formed on the first conducting type source layer and the second conducting type base layer, and a gate electrode formed in contact with the first conducting type source layer, the second conducting type base layer and the semiconductor substrate through a gate insulating film and a lateral semiconductor device having an insulating layer formed in a region of the surface of the semiconductor substrate different from the second conducting type base layer, and a polycrystalline semiconductor layer formed on the insulating layer and having a first conducting type region and a second conducting type region, wherein the first conducting type source layer of the vertical semiconductor device and the first conducting type region of the polycrystalline semiconductor layer are simultaneously formed.

Claims

1. A method of manufacturing a semiconductor apparatus having a vertical type semiconductor device and a lateral type semiconductor device, wherein said method includes, fabricating said vertical type semiconductor device on a first conducting type semiconductor substrate by steps comprising,

forming a drain layer on a first surface of said first conductive type semiconductor substrate,

selectively forming a second conducting type base layer in a second surface of said semiconductor substrate opposite to said drain layer,

forming a first gate insulating film using a thermal process in contact with said second conducting type base layer and a portion of said first conducting type semiconductor substrate,

forming a first gate electrode via said first gate insulating film opposite to said second conducting type base layer and said portion of said first conducting type semiconductor substrate by doping an impurity,

selectively forming a first conducting type source layer in the surface of said second conducting type base layer,

forming a first source electrode over said first conducting type source layer and a portion of said second conducting type base layer, and

forming a first drain electrode over an outer surface of said drain layer;

and

fabricating said lateral type semiconducting device by steps comprising,

forming an insulating layer in a region of said second surface of said first conducting type semiconductor substrate,

forming a polycrystalline semiconductor layer on said insulating layer,

forming a second gate insulating film on said polycrystalline semiconductor layer using the same thermal process as that for said first gate insulating film, and

selectively forming a second gate electrode over said second gate insulating film on said polycrystalline semiconductor layer using the same doping steps as that used for doping said first gate electrode.

2. The method according to claim 1, further including forming said first gate insulating film with a thickness of 600 Å

or less.

3. The method according to claim 1, further including forming said first gate insulating film with a thickness of 300 Å

or less.

4. The method according to claim 1, further comprising the steps of:

forming a second conducting type contact layer in the surface of said second conducting type base layer, which has a carrier density higher than that of said second conducting type base layer using doping of an impurity, and

forming a second conducting type region in said polycrystalline semiconductor layer using the same doping process as that for doping said second conducting type contact layer.

5. The method according to claim 1, further comprising the steps of:

forming a second conductivity type base region in said polycrystalline semiconductor layer,

selectively forming a first conductivity type drain region in said second conductivity type base region,

forming a second drain electrode over said first conductivity type drain region,

selectively forming a first conductivity type source region in said polycrystalline semiconductor layer in such a manner that said first conductivity type source region is separated from said first conductivity type drain region by said second conductivity type base region, and

forming a second source electrode over said first conductivity type source region.

6. The method according to claim 5, further including forming said first conducting type source layer of said vertical semiconductor device and said first conductivity type source region of said lateral semiconductor device by simultaneously doping an impurity.