Method of forming a via hole structure including CVD tungsten silicide barrier layer
First Claim
1. A method of forming a via hole structure in a semiconductor device, comprising the steps of:
- (a) forming one or more dielectric layers over a substrate surface comprising an aluminum or aluminum alloy metal pattern;
(b) depositing a spin-on-glass layer over the one or more dielectric layers;
(c) forming one or more additional dielectric layers over the spin-on-glass layer;
(d) forming a via hole through the one or more additional dielectric layers, the spin-on-glass layer and the one or more dielectric layers, the via hole extending to a top surface of the aluminum or aluminum alloy metal pattern and being bounded by a sidewall comprising the one or more dielectric layers, the spin-on-glass layer and the one or more additional dielectric layers;
(e) forming a titaniurn layer, a titanium nitride layer or a titanium/titanium nitride bilayer on the sidewall and on the aluminum or aluminum alloy metal pattern within the via hole, said layer having a thickness of from about 100 to 2000 Å
;
(f) depositing a tungsten silicide layer on the layer formed in step (e), the tungsten silicide layer being formed by chemical vapor deposition and having a thickness of from about 50 to 700 Å
; and
filling the via hole with tungsten by depositing tungsten on the tungsten silicide, the tungsten silicide layer suppresses outgassing of the spin-on-glass layer during deposition of the tungsten.
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Abstract
The invention relates to integrated circuits and to via hole structures which include a tungsten silicide barrier layer and to methods of forming such via hole structures. In an exemplary embodiment, a metal layer is formed on a sidewall and a bottom surface of the via hole, a WSix barrier layer is formed on the first metal layer by chemical vapor deposition and the via hole is subsequently filled with a metal. The tungsten silicide barrier layer effectively suppresses device degradation resulting from the release of gaseous species from the sidewall of the via hole during plug formation. Semiconductor devices can thus be fabricated which are immune or less susceptible to metal open failures due to incomplete via filling.
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Citations
11 Claims
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1. A method of forming a via hole structure in a semiconductor device, comprising the steps of:
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(a) forming one or more dielectric layers over a substrate surface comprising an aluminum or aluminum alloy metal pattern; (b) depositing a spin-on-glass layer over the one or more dielectric layers; (c) forming one or more additional dielectric layers over the spin-on-glass layer; (d) forming a via hole through the one or more additional dielectric layers, the spin-on-glass layer and the one or more dielectric layers, the via hole extending to a top surface of the aluminum or aluminum alloy metal pattern and being bounded by a sidewall comprising the one or more dielectric layers, the spin-on-glass layer and the one or more additional dielectric layers; (e) forming a titaniurn layer, a titanium nitride layer or a titanium/titanium nitride bilayer on the sidewall and on the aluminum or aluminum alloy metal pattern within the via hole, said layer having a thickness of from about 100 to 2000 Å
;(f) depositing a tungsten silicide layer on the layer formed in step (e), the tungsten silicide layer being formed by chemical vapor deposition and having a thickness of from about 50 to 700 Å
; andfilling the via hole with tungsten by depositing tungsten on the tungsten silicide, the tungsten silicide layer suppresses outgassing of the spin-on-glass layer during deposition of the tungsten. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification