Method of measuring electrical characteristics of semiconductor circuit in wafer state and semiconductor device for the same

• US 5,986,282 A
• Filed: 10/24/1997
• Issued: 11/16/1999
• Est. Priority Date: 02/18/1997
• Status: Expired due to Fees

• Current Assignee: Honda Giken Kogyo Kabushiki Kaisha (Honda Motor Company)
• Original Assignee: Honda Giken Kogyo Kabushiki Kaisha (Honda Motor Company)
• Inventors: Seki, Hideo
• Primary Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/957,157
• Time in Patent Office: 753 Days
• Field of Search: 438/15, 324/765, 257/48
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A plurality of semiconductor circuits provided on a semiconductor wafer are arranged in a plurality of rows. The plurality of semiconductor circuits of each row are connected in series through first and second conductive layers provided between adjacent two of the semiconductor circuits of each row. The plurality of semiconductor circuits are connected to power supply terminals provided on the semiconductor wafer. The first and second conductive layers may be provided separately from the higher and lower voltage side power supply lines, or one of the first and second conductive layers may be common to one of the higher and lower voltage side power supply lines. The power supply is connected to the power supply terminals and the plurality of semiconductor circuits is aged. After the aging, the power supply is disconnected from the power supply terminals. In this state, electrical characteristics of each semiconductor circuit is measured in a state in which the semiconductor circuits is isolated from the other semiconductor circuits.

Claims

1. A semiconductor device comprising:

a plurality of semiconductor circuits formed on a semiconductor wafer, wherein each of said plurality of semiconductor circuits includes a higher voltage side power supply line, a lower voltage side power supply line and a control pattern section; and

first and second semiconductor conductive layers provided between adjacent two of said plurality of semiconductor circuits in said semiconductor wafer to overlap said two semiconductor circuits in parts of said first and second semiconductor conductive layers, and

wherein said higher voltage side power supply line and said lower voltage side power supply line of each of said adjacent two semiconductor circuits of said plurality of semiconductor circuits are respectively connected to said corresponding first semiconductor conductive layers and said corresponding second semiconductor conductive layers such that said plurality of semiconductor circuits are connected in series through said higher and lower voltage side power supply lines and said first and second conductive layers, and

wherein said control pattern section and said first and second semiconductor conductive layers corresponding to each of said plurality of semiconductor circuits form a MOSFET structure.

2. A semiconductor device according to claim 1, wherein each of said higher and lower voltage side power supply lines comprises at least one of a metal wiring layer and a conductive semiconductor layer.

3. A semiconductor device according to claim 1, further comprising pads provided on said semiconductor wafer, for supplying higher and lower voltages to said plurality of semiconductor circuits.

4. A semiconductor device according to claim 1, wherein when a predetermined voltage is applied to said control pattern section, depletion layers are formed in said first and second semiconductor conductive layers corresponding to said control pattern section to electrically disconnect said semiconductor circuit corresponding to said control pattern section from the other semiconductor circuits.

5. A semiconductor device according to claim 1, wherein said control pattern section Includes one control pattern, and each of said plurality of semiconductor circuits is electrically isolated from the other semiconductor circuits by applying a predetermined voltage to said control pattern of said adjacent two semiconductor circuits.

6. A semiconductor device according to claim 1, wherein said control pattern section includes a first pattern and a second pattern, and each of said plurality of semiconductor circuits is electrically isolated from the other semiconductor circuits by applying a predetermined voltage to said first pattern and the second pattern.

7. A semiconductor device according to claim 1, wherein said first and second semiconductor conductive layers are formed in a semiconductor conductive layer of a conductive type which is different from said first and second semiconductor conductive layers.

8. A semiconductor device comprising:

a plurality of semiconductor circuits formed on a semiconductor wafer, wherein each of said plurality of semiconductor circuits includes a higher voltage side power supply line, a lower voltage side power supply line and a control pattern; and

first and second semiconductor conductive layers, said first semiconductor conductive layer being provided between adjacent two of said plurality of semiconductor circuits to overlap said two of said plurality of semiconductor circuits in a part of said first semiconductor conductive layer, and said second semiconductor layer being provided in common to said plurality of semiconductor circuits, and

wherein one of said higher voltage side power supply line and said lower voltage side power supply line of each of said adjacent two semiconductor circuits of said plurality of semiconductor circuits is connected to said corresponding first semiconductor conductive layer and the other is connected to said second semiconductor conductive layer such that said plurality of semiconductor circuits are connected in series using said first and second semiconductor conductive layers, and

wherein said control pattern and said first and second semiconductor conductive layers of each of said plurality of semiconductor circuits form a MOSFET structure.

9. A semiconductor device according to claim 8, wherein each of said higher and lower voltage side power supply lines comprises at least one of a metal wiring layer and a conductive semiconductor layer.

10. A semiconductor device according to claim 8, further comprising pads provided on said semiconductor wafer, for supplying higher and lower voltages to said plurality of semiconductor circuits.

11. A semiconductor device according to claim 8, wherein when a predetermined voltage is applied to said control pattern, a depletion layer is formed in said first semiconductor conductive layer corresponding to said control pattern to electrically disconnect corresponding to said control pattern from the other semiconductor circuits.

12. A semiconductor device according to claim 8, wherein each of said plurality of semiconductor circuits is electrically isolated from the other semiconductor circuits by applying a predetermined voltage to said control patterns of said adjacent two semiconductor circuits.

13. A semiconductor device according to claim 8, wherein each of said plurality of semiconductor circuits includes an additional control pattern, and said each of said plurality of semiconductor circuits is electrically isolated from the other semiconductor circuits by applying a predetermined voltage to said control pattern and said additional control pattern.

14. A semiconductor device according to claim 8, wherein said first semiconductor conductive layer is formed in a semiconductor conductive layer of a conductive type which is different from that of said first semiconductor conductive layer.