Punch-through prevention in trenched DMOS with poly-silicon layer covering trench corners

• US 5,986,304 A
• Filed: 01/13/1997
• Issued: 11/16/1999
• Est. Priority Date: 01/13/1997
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Megamos Corporation
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong, Lin, True-Lon
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US08/782,368
• Time in Patent Office: 1,037 Days
• Field of Search: 257/328, 257/330-332, 257/334, 257/347, 257/356, 257/203-223, 257/228, 257/472, 257/476, 438/203, 438/100, 438/225, 438/228, 438/361-362, 438/497, 438/498, 438/499
• US Class Current: 257/330
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The present invention includes a substrate of a first conductivity type having a top surface including at least two intersecting trenches disposed therein with an insulating layer lining the trenches and a conductive material filling the trenches. The transistor also includes a source region of the first conductivity type extending from the top surface of the substrate adjacent to the trenches toward the substrate. The transistor further has a body region of a second conductivity type of opposite polarity from the first conductivity type, the body region extends from the top surface adjacent from the trenches to the substrate and surrounding the source region. The conductive material filling the trenches including punch-through suppressing blocks covering corners of the cell defined by the intersecting trenches wherein the source region disposed underneath the corners immediately next to the trenches having a lower net concentration of impurities of the first conductivity type than remaining portion of the source region.

Claims

1. A transistor cell comprising:

a substrate of a first conductivity type having a top surface including at least two intersecting trenches disposed therein;

an insulating layer lining said trenches;

a conductive material filling said trenches;

a source region of said first conductivity type extending from said top surface of said substrate adjacent to said trenches toward said substrate;

a body region of a second conductivity type of opposite polarity from said first conductivity type, said body region extends from said top surface adjacent from said trenches to said substrate and surrounding said source region; and

said conductive material filling said trenches and partially rising above said trenches only near corners defined by said intersecting trenches for covering said corners thus constituting trench-corner source implant blocking blocks for reducing a net dopant concentration of said source region underneath said blocking blocks immediately next to said corner defined by said intersecting trenches having a lower net concentration of impurities of said first conductivity type than remaining portion of said source region.

2. The transistor cell of claim 1 wherein:

each of said trench-corner source implant blocking blocks rising partially above said trenches near said corners having a length and a width ranging approximately from 0.1 to 0.5 microns for covering an area only surrounding said corners.

3. The transistor cell of claim 1 wherein:

said cell includes four corners each defined by two of said intersecting trenches and covered by said trench-corner source implant blocking blocks rising partially above said trenches near said four corners.

5. The transistor cell of claim 1 further comprising:

a contact-means for contacting body-region of said second conductivity type disposed at a center portion of said source region having a higher dopant concentration of said second conductivity type and extending from said top surface to said body region in said substrate for providing a body contact means therein.

6. The transistor cell of claim 1 wherein:

said source region extending to said top surface and defining a rectangle thereon in contact with said trenches with said corners defined by intersections of trenches overlaid by said trench-corner source implant blocking blocks partially rising above said trenches near said corners.

7. The transistor cell of claim 1 further comprising:

a plurality of similar cells arranged in rows and including a trench separating two neighboring rows thus constituting a gate finger connecting said conductive material filling said trenches in each of said rows functioning as a trenched gate for each of said cells.

8. The transistor cell of claim 7 further comprising:

additional trench-corner source implant blocking blocks partially rising above said trenches only near said corners for covering said corners defined by said gate finger intersecting said trenches defining said row of cells.

4. A transistor cell comprising:

a substrate of a first conductivity type having a top surface including at least two intersecting trenches disposed therein;

an insulating layer lining said trenches;

a conductive material filling said trenches;

a source region of said first conductivity type extending from said top surface of said substrate adjacent to said trenches toward said substrate;

a body region of a second conductivity type of opposite polarity from said first conductivity type, said body region extends from said top surface adjacent from said trenches to said substrate and surrounding said source region;

said conductive material filling said trenches and partially rising above said trenches only near corners defined by said intersecting trenches for covering said corners thus constituting trench-corner source implant blocking blocks for reducing a net dopant concentration of said source region underneath said blocking blocks immediately next to said corner defined by said intersecting trenches having a lower net concentration of impurities of said first conductivity type than remaining portion of said source region; and

said body region adjacent to said source region underneath said trench-corner source implant blocking blocks having a higher rate of net-second-conductivity-impurity-concentration increase along a depth direction extending downwardly from said top surface than a remaining portion of said body region whereby a punch-through is suppressed in said trench near said corner.

9. A transistor cell comprising:

a substrate of a first conductivity type having a top surface including at least two intersecting trenches disposed therein;

an insulating layer lining said trenches;

a conductive material filling said trenches;

a source region of said first conductivity type extending from said top surface of said substrate adjacent to said trenches toward said substrate;

a body region of a second conductivity type of opposite polarity from said first conductivity type, said body region extends from said top surface adjacent from said trenches to said substrate and surrounding said source region;

said conductive material filling said trenches and partially rising above said trenches only near corners defined by said intersecting trenches for covering said corners thus constituting trench-corner source implant blocking blocks for reducing a net dopant concentration of said source region underneath said blocking blocks immediately next to said corner defined by said intersecting trenches having a lower net concentration of impurities of said first conductivity type than remaining portion of said source region;

said body region adjacent to said source region underneath said trench-corner source implant blocking blocks having a higher rate of net-second-conductivity-impurity-concentration increase along a depth direction extending downwardly from said top surface than a remaining portion of said body region whereby a punch-through is suppressed in said trench near said corner.