Programmable integrated circuit having L-shaped programming power buses that extend along sides of the integrated circuit

• US 5,986,469 A
• Filed: 09/17/1997
• Issued: 11/16/1999
• Est. Priority Date: 06/21/1996
• Status: Expired due to Term

• Current Assignee: QuickLogic Corporation
• Original Assignee: QuickLogic Corporation
• Inventors: Eaton, David D., Kolze, Paige A., Apland, James M.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US08/932,890
• Time in Patent Office: 790 Days
• Field of Search: 326/38-41, 326/47
• US Class Current: 326/41
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A programmable integrated circuit (see FIG. 9) has a plurality of L-shaped programming power buses (for example, 126, 130, 129 and 127) that extend along sides of the integrated circuit. Each L-shaped programming power bus extends along two adjacent sides of the integrated circuit such that legs of two L-shaped programming power buses extend along each of the sides. There are four pluralities of programming drivers (for example, 110, 117, 115 and 112), one plurality being associated with each of the four sides. There are also four programming current multiplexers (for example, 118, 125, 123 and 120), one associated with each of the sides. A programming driver of one of the plurality of programming drivers is selectively couplable to one of the two L-shaped programming power bus legs that extends along the associated side of the integrated circuit via the programming current multiplexer associated with that side. Additional pluralities of programming drivers and additional programming current multiplexers can be provided.

Claims

1. A programmable integrated circuit having a rectangular shape with a first side, a second side, a third side and a fourth side, the first and third sides being parallel with respect to one another, the second and fourth sides being parallel with respect to one another and perpendicular with respect to the first and third sides, comprising:

an array comprising a plurality of logic modules and a programmable interconnect structure including antifuses;

first through fourth programming power buses, the first programming power bus extending adjacent and parallel to the first side and also extending adjacent and parallel to the second side, the second programming power bus extending adjacent and parallel to the second side and also extending adjacent and parallel to the third side, the third programming power bus extending adjacent and parallel to the third side and also extending adjacent and parallel to the fourth side, the fourth programming power bus extending adjacent and parallel to the fourth side and also extending adjacent and parallel to the first side; and

first through fourth pluralities of programming drivers, the programming drivers of the first plurality being selectively couplable in a programming mode to either the first or fourth programming power bus, each of the programming drivers of the second plurality being selectively couplable in a programming mode to either the first or second programming power bus, each of the programming drivers of the third plurality being selectively couplable in a programming mode to either the second or third programming power bus, and each of the programming drivers of the fourth plurality being selectively couplable in a programming mode to either the third or fourth programming power bus.

2. The programmable integrated circuit of claim 1, further comprising:

first through fourth programming voltage terminals, the first programming voltage terminal being coupled to the first programming power bus, the second programming voltage terminal being coupled to the second programming power bus, the third programming voltage terminal being coupled to the third programming power bus, the fourth programming voltage terminal being coupled to the fourth programming power bus.

3. The programmable integrated circuit of claim 2, wherein the first programming voltage terminal is disposed adjacent a first corner of the programmable integrated circuit, the second programming voltage terminal is disposed adjacent a second corner of the programmable integrated circuit, the third programming voltage terminal is disposed adjacent a third corner of the programmable integrated circuit, and the fourth programming voltage terminal is disposed adjacent a fourth corner of the programmable integrated circuit.

4. The programmable integrated circuit of claim 1, further comprising:

a ground bus which extends around the programmable integrated circuit adjacent the first, second, third and fourth sides.

5. The programmable integrated circuit of claim 1 further comprising:

a ground bus, the programming drivers of the first plurality also being selectively couplable in a programming mode to the ground bus, each of the programming drivers of the second plurality also being selectively couplable in a programming mode to the ground bus, each of the programming drivers of the third plurality also being selectively couplable in a programming mode to the ground bus, and each of the programming drivers of the fourth plurality also being selectively couplable in a programming mode to the ground bus.

6. The programmable integrated circuit of claim 1, further comprising:

fifth through eighth pluralities of programming drivers, the programming drivers of the fifth plurality being selectively couplable in a programming mode to either the first or fourth programming power bus, each of the programming drivers of the sixth plurality being selectively couplable in a programming mode to either the first or second programming power bus, each of the programming drivers of the seventh plurality being selectively couplable in a programming mode to either the second or third programming power bus, and each of the programming drivers of the eighth plurality being selectively couplable in a programming mode to either the third or fourth programming power bus.