Fully switched, class-B, high speed current amplifier driver

• US 5,986,479 A
• Filed: 05/05/1997
• Issued: 11/16/1999
• Est. Priority Date: 05/05/1997
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Mohan, Jitendra
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US08/841,813
• Time in Patent Office: 925 Days
• Field of Search: 326/86, 326/83, 326/89, 326/115, 326/127, 326/126, 327/108, 327/109, 327/489, 327/490, 327/492, 330/253, 330/257
• US Class Current: 326/115
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors

Abstract

A current amplifier driver capable of driving both 10 Base-T signalling and 100 Base signalling in a Local Area Network (LAN) includes one constant current source. A voltage controlled switch is contained in each of four vertical segment of an H-bridge circuit. Two voltage signals are applied to the switches to control the direction of current from a constant current source across a load. When one of the voltage signals is high, the other is low and two switches of the four switches turn on. The current amplifier driver sinks the constant current in a first direction, such that a voltage drop across the output nodes is positive. When the other voltage signal is high the switches that were on turn off, and the other two switches turn on to sink the constant current across the load in the opposite direction, such that a voltage drop across the output nodes is negative. When both voltage signals are low, all four switches turn off, and the output voltage is zero. In this manner, a differential signal is generated across a resistive load.

Claims

1. An apparatus including a current driving circuit for providing a tri-level differential signal to a load, said current amplifier driver circuit comprising:

first and second output nodes configured to couple to an external circuit and convey first, second and zero output drive signals;

a first resistive circuit, coupled to said first output node and configured to receive a first control signal;

a second resistive circuit, coupled to said first output node and configured to receive a second control signal;

a third resistive circuit, coupled to said second output node and configured to receive said second control signal;

a fourth resistive circuit, coupled to said second output node and configured to receive said first control signal;

an input transistor coupled to the second resistive circuit to form a first switching current source, and coupled to the fourth resistive circuit to form a second switching current source, said first and second switching current sources configured to receive a first input signal and in accordance therewith provide a drive signal; and

a buffer circuit coupled between the input transistor and the first and fourth resistive circuits,

wherein;

said first and second control signals have active and inactive signal states;

said first and fourth resistive circuits convey said drive signal in a first direction in accordance with said first control signal active state, thereby generating said first output drive signal;

said second and third resistive circuits convey said drive signal in a second direction in accordance with said second control signal active state, thereby generating said second output drive signal;

said first, second, third and fourth resistive circuits cease conveying said drive signal when each of said first and second control signals have an inactive signal state, thereby generating a zero output drive signal; and

said first, second and zero output drive signals together form at said first and second output nodes a tri-level differential output signal which is proportional to a difference of said first control signal and said second control signal.

2. The apparatus of claim 1, wherein said first and second resistive circuits comprise first and second selectively conductive circuits with first and second conductivities which correspond to said active and inactive states of said first and second control signals, respectively, and wherein said first conductivity is higher than said second conductivity.

3. The apparatus of claim 1, wherein said third and fourth resistive circuits comprise first and second selectively conductive circuits with first and second conductivities which correspond to said active and inactive states of said second and first control signals, respectively, and wherein said first conductivity is higher than said second conductivity.

4. The apparatus of claim 1, further comprising a fifth resistive circuit coupled between said first and second output nodes and configured to further convey said first, second and zero output drive signals and thereby provide said tri-level differential output signal.

5. A method of providing a tri-level differential signal to a load, said method comprising the steps of:

generating a drive current;

receiving a first control signal and a second control signal, said first and second control signals having active and inactive signal states, and in accordance therewith generating first, second and third output drive signals;

sinking said drive current in a first direction when said first control signal has an active signal state and said second control signal has an inactive signal state, thereby generating the first output drive signal;

sinking said drive current in a second direction when said first control signal has an inactive signal state and said second control signal has an active signal state, thereby generating the second output drive signal;

suspending said drive current when each of said first and second control signals have an inactive signal state, thereby generating the third output drive signal; and

conveying said first, second and third output drive signals via first and second output nodes which are coupled to an external circuit, wherein said first, second and third output drive signals together form at said first and second output nodes a tri-level differential output signal which is proportional to a difference of said first control signal and said second control signal.

6. The method of claim 5, wherein the step of suspending said drive current when each of said first and second control signals have an inactive signal state, thereby generating the third output drive signal comprises ceasing to conduct said drive current when said first and second control signals have an inactive signal state, thereby generating the third output signal having a zero value.

7. The method of claim 5, wherein said step of conveying said first, second and third output drive signals via first and second output nodes which are coupled to an external circuit comprises:

establishing first and second conductivities of first and second selectively conductive circuits, wherein said first conductivity is higher than said second conductivity;

establishing first and second conductivities of third and fourth selectively conductive circuits, wherein said first conductivity is higher than said second conductivity;

conveying said first output drive signal to said first output node via said first and second selectively conductive circuits, when said first and second selectively conductive circuits have said first conductivity;

conveying said second output drive signal to said second output node via third and fourth selectively conductive circuits, when said third and fourth selectively conductive circuits have said first conductivity; and

conveying said third output drive signal to said first and second output nodes when said first, second, third and fourth selectively conductive circuits have said second conductivity.

8. A method of providing a tri-level differential signal to a load, said method comprising the steps of:

generating a drive current;

activating a first switching circuit and in accordance therewith conducting said drive current in a first direction, thereby generating a first output drive signal;

activating a second switching circuit and in accordance therewith conducting said drive current in a second direction, thereby generating a second output drive signal;

deactivating said first and second switching circuits and in accordance therewith suspending said drive current, thereby generating a third output drive signal having a zero value; and

conveying said first, second and third output drive signals via first and second output nodes which are coupled to an external circuit, wherein said first, second and third output drive signals together form at said first and second output nodes a tri-level differential output signal.