Direct digital frequency systhesizer

• US 5,986,483 A
• Filed: 12/01/1997
• Issued: 11/16/1999
• Est. Priority Date: 10/02/1997
• Status: Expired due to Term

• Current Assignee: National Science Council
• Original Assignee: National Science Council
• Inventors: Yu, Tzong-Bang, Tsao, Hen-Wai, Liu, Shen-Iuan
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US08/980,655
• Time in Patent Office: 715 Days
• Field of Search: 327/105, 327/115, 327/116, 327/106, 327/107, 327/141, 364/721, 364/718
• US Class Current: 327/107
• CPC Class Codes: G06F 1/0356 by using two or more smaller tables, e.g. addressed by parts of the argument
• CPC Class Codes: H04L 27/2017 in which the phase changes are non-linear, e.g. generalized and Gaussian minimum shift keying, tamed frequency modulation H04L27/201 takes precedence

Abstract

A direct digital frequency synthesizer outputting a sine signal is disclosed, comprising an accumulator, a symmetry circuit, a coarse circuit, a fine circuit and a sign circuit, wherein the accumulator sequentially outputs a sample address according to a frequency control signal. The symmetry circuit takes the complement of the sample address according to a first clock, the period of the first clock being twice the period of the first MSB of the sample address, to obtain a symmetric sample address represented by N bits. The coarse circuit connected to the symmetry circuit outputs the first M MSBs of the symmetric sample address as the first M MSBs of the sine signal. The fine circuit predicts the last N-M LSBs of the sine signal from the last N-M LSBs of the symmetric sample address according to the first M MSBs of the symmetric sample address of the coarse circuit. Then, the sign circuit outputs a sign bit of the sine signal according to a second clock, the period of the second clock being four times that of the period of the first MSB of the symmetric sample address.

Claims

1. A direct digital frequency synthesizer to output a sine signal, comprising:

an accumulator sequentially outputting a sample address with a periodic MSB according to a frequency control signal, the sample address represented by N bits, wherein N is an integer;

a symmetry circuit controlled by a first clock with a period twice that of the MSB of the sample address to produce a symmetry sample address by producing a complement of the sample address;

a coarse circuit connected to the symmetry circuit to output a first M bits of the symmetry sample address as a first M bits of the sine signal, wherein M is an integer that is less than N;

a fine circuit connected to the symmetry circuit to predict a last N-M bits of the sine signal from a last N-M bits of the symmetry sample address according to the first M bits of the symmetry sample address; and

a sign circuit connected to the accumulator for receiving said sample address, the coarse circuit and the fine circuit, controlled by a second clock with a period four times that of the MSB of the symmetry sample address to output said sine signal and a sign bit of the sine signal.

2. The direct digital frequency synthesizer as claimed in claim 1, wherein the accumulator is a 16-bit accumulator having an output, the sample address is a last 12 bits of the accumulator output, and the first clock is a bit preceding the first bit of the sample address.

3. The direct digital frequency synthesizer as claimed in claim 2, wherein the coarse circuit receives a first 3 bits of the symmetric sample address as a first 3 bits of the sine signal.

4. The direct digital frequency synthesizer as claimed in claim 2, wherein the sign circuit is controlled by a bit preceding the first bit of the symmetry sample address by two bits to provide the sign bit of the sine signal.

5. The direct digital frequency synthesizer as claimed in claim 4, wherein the sign circuit comprises a multiplexer controlled by the second clock to provide the sign bit of the sine signal.

6. The direct digital frequency synthesizer as claimed in claim 2, wherein the fine circuit predicts a last 9 bits of the sine signal from a last 9 bits of the symmetric sample address according to a first 3 bits of the symmetric sample address.

7. The direct digital frequency synthesizer as claimed in claim 6, wherein the fine circuit predicts the last 9 bits of the sine signal from the last 9 bits of the symmetric sample address by:

space="preserve" listing-type="equation">g(x)=Ai*x+Di

where x is the last 9 bits of the symmetric sample address, Ai and Di are constants determined by the first 3 bits of the symmetric sample address, and g(x) is the predicted last 9 bits of the sine signal.

8. The direct digital frequency synthesizer as claimed in claim 7, wherein the fine circuit comprises a plurality of shifters and a plurality of adders.

9. The direct digital frequency synthesizer as claimed in claim 1, further comprising a first register to store the sample address from the accumulator and output the sample address to the symmetry circuit in synchronization with a reference clock.

10. The direct digital frequency synthesizer as claimed in claim 9, further comprising a second register to store the sign bit from the sign circuit and output the sign bit in synchronization with the reference clock.

11. The direct digital frequency synthesizer as claimed in claim 1, wherein the the fine circuit is structured in a pipeline fashion.

12. A method of producing a sine signal by direct digital frequency synthesis comprising the steps of:

sequentially generating a sample address with a periodic MSB according to a frequency control signal, the sample address being represented by N bits, wherein N is an integer;

generating a symmetry sample address by producing a complement of the sample address;

outputting a first M bits of the symmetry sample address as a first M bits of the sine signal, wherein M is an integer that is less than N;

predicting a last N-M bits of the sine signal from a last N-M bits of the symmetry sample address according to the first M bits of the symmetry sample address in accordance with a linear approximation; and

generating the sine signal based on the outputted M bits and the predicted N-M bits.