Low voltage, beta immune variable gain amplifier with high supply voltage rejection

• US 5,986,501 A
• Filed: 06/30/1998
• Issued: 11/16/1999
• Est. Priority Date: 06/30/1998
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Rafati, Hamid, Eschauzier, Rudolphe Gustave
• Primary Examiner(s): Lee, Benny
• Assistant Examiner(s): Nguyen, Patricia T.
• Application Number:
  US09/107,529
• Time in Patent Office: 504 Days
• Field of Search: 330/254, 330/252, 330/261, 327/359
• US Class Current: 330/254
• CPC Class Codes: H03G 1/0023 in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence

Abstract

A variable gain amplifier includes a Gilbert cell multiplier cell having a pair of bipolar input transistors and a pair of bipolar output transistors. A bias circuit provides a first bias current to the input transistors and a second bias current to the output transistors, the ratio of the second to the first bias current determining the gain of the multiplier cell. The bias circuit couples the first and second bias currents to the emitters of the input and output transistors and references these currents to ground, which provides excellent supply rejection. Additionally, high beta immunity is achieved by increasing the ratio of the second bias current to the first bias current by subtracting a current from the first bias current substantially equal to the base currents of the output transistors.

Claims

1. An amplifier for operation between a first supply and a second supply having a lower potential than the first supply, comprising:

a) a current multiplier circuit including

a first, differentially coupled input pair of transistors each having a base for receiving an input current of the multiplier cell, a collector coupled to the first supply, an emitter and a common base-collector junction;

a second, differentially coupled output pair of transistors each having a base coupled to said base of a respective input transistor, a collector for output ting an output current of the multiplier circuit, and an emitter; and

b) a bias circuit which biases the emitters of said input transistors with a first bias current and the emitters of said output transistors with a second bias current to control the ratio of the differential output current to the differential input current at a selected value, wherein the ratio of (i) the second bias current and (ii) the first bias current minus a current substantially equal to the base currents of the output transistors is substantially equal to the selected value of said ratio of the differential output currents to the differential input currents.

2. An amplifier according to claim 1, wherein said bias circuit generates a first current, subtracts from the first current a third current substantially equal to the base currents of said output pair of transistors, and biases said emitters of said input transistors with said first bias current being equal to said first current minus said third current.

3. An amplifier circuit according to claim 2, wherein said bias circuit includes a first current source, and a first current mirror having an input fed by said first current source and an output, coupled to said emitters of said input transistors of said multiplier circuit, which outputs said first current.

4. An amplifier according to claim 3, wherein said bias circuit includes a second current source, and a second current mirror having an input fed by said second current source and an output, coupled to said emitters of said output transistors of said multiplier circuit, which outputs said second current.

5. An amplifier according to claim 4, wherein said second current mirror comprises first and second current mirror transistors having a common base junction, and said bias circuit further comprises a third current mirror having an input coupled to said common base junction of said second current mirror and an output coupled to said output of said first current mirror, said third current mirror subtracting from said first current the third current equal to the base currents of said first and second current mirror transistors.

6. An amplifier according to claim 4, wherein said first current mirror includes third and fourth current mirror transistors, said third current mirror includes fifth and sixth current mirror transistors, and the transistors of the output pair of transistors and of each of the first, second and third current mirrors have substantially equal gain factors (β

).

7. An amplifier according to claim 2, wherein said bias circuit includes a second current source, and a second current mirror having an input fed by said second current source and an output which output s said second current.

8. A variable gain amplifier for operation between a first supply and a second supply having a lower potential than the first supply, said variable gain amplifier comprising:

a) a multiplier circuit comprising

differential input terminals which receive a differential input current;

differential output terminals which output a differential output current;

a pair of bipolar input transistors each having a base coupled to a respective one of said differential input terminals, a collector coupled to a first supply, an emitter, and a common base-collector junction;

a pair of bipolar output transistors each having a base commonly coupled, respectively, to said base of one of said input transistors and one of said differential input terminals, a collector coupled to a respective one of said differential output terminals, and an emitter coupled to said second supply; and

b) a biasing circuit comprising

first and second current sources;

a first, input current mirror having an input coupled to the first current source, and an output coupled to said emitter of each of said input pair of transistors, said output outputting a first, said input current mirror having a first pair of current mirror transistors having bases coupled to each other,

a second, output current mirror having an input coupled to the second current source and an output coupled to each emitter of said output pair of transistors to provide a second, bias current to each of said output pair of transistors, said output current mirror having a second pair of current mirror transistors having bases coupled to each other, and

a third current mirror, said third current mirror having an input coupled to said bases of said second pair of current mirror transistors, and an output coupled to said output of said first current mirror, said third current mirrors subtracting from said output of said first current mirror a third current substantially equal to the base currents of said second pair of current mirror transistors, said first current less said third current equaling a first bias current applied to said emitters of said input pair of transistors.

9. A variable gain amplifier according to claim 8, wherein said biasing circuit further includes (i) a first beta helper transistor having a base coupled to the second current source, a collector coupled to the input of the third current mirror and an emitter coupled to the bases of each of said second pair of current mirror transistors and (ii) a second beta helper transistor having a base coupled to the first current source, a collector coupled to the first voltage supply and an emitter coupled to the bases of each of said first pair of current mirror transistors.

10. A variable gain amplifier according to claim 8, wherein said biasing circuit further comprises:

(i) a fourth current mirror and a first beta helper transistor, said fourth current mirror having an input coupled to said bases of said first pair of current mirror transistors and an output, said first beta helper transistor having a base coupled to said first current source, a collector coupled to said output of said fourth current mirror and an emitter coupled to the second lower supply; and

(ii) a fifth current mirror and a second beta helper transistor, said fifth current mirror having an input coupled to said bases of said second pair of current mirror transistors and an output, said second beta helper transistor having a base coupled to said second current source and an emitter coupled to said second power supply.

11. A method of biasing a multiplier cell having

a pair of bipolar input transistors each having a base coupled to a respective one of said differential input terminals, a collector coupled to a first supply, an emitter, and a common base-collector;

and

a pair of bipolar output transistors each having a base commonly coupled, respectively, to one of said input transistors and one of said differential input terminals, a collector coupled to a respective one of said differential output terminals, and an emitter,

said method comprising the steps of;

controlling the gain of the multiplier cell equal to a ratio between the output currents and the input currents by biasing the emitters of said input transistors with a first bias current and the emitters of said output transistors with a second bias current, wherein the ratio of (ii) the second bias current and (ii) the first bias current minus a current substantially equal to the base currents of the output transistors is substantially equal to said ratio of the output currents to the input currents.

12. A method according to claim 11, wherein said controlling step comprises:

generating a first current and a second current, the ratio of the second current to the first current corresponding to a desired current gain ratio between the output current and the input current of the multiplier cell;

generating a third current by subtracting from the first current a current at least substantially equal to the sum of the base currents of the output transistors; and

biasing said emitters of said input transistors with said third current and the emitters of said output transistors with said second current.