Accelerated graphics port read transaction merging

• US 5,986,677 A
• Filed: 09/30/1997
• Issued: 11/16/1999
• Est. Priority Date: 09/30/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Jones, Phillip M., Santos, Gregory N., Horan, Ronald T.
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/941,859
• Time in Patent Office: 777 Days
• Field of Search: 345/520, 345/501-503, 345/521, 710/126-129
• US Class Current: 345/531
• CPC Class Codes: G06F 13/1631 through address comparison

Abstract

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as an AGP graphics controller, and a host processor and computer system memory wherein AGP transaction read requests are merged from the AGP graphics controller and retired when these requests are within a cacheline of the memory being accessed. The core logic chipset will request a memory cacheline read as it begins processing a current AGP transaction read request. Once the memory read access is initiated, the transaction read request will be popped off an AGP request queue in order to evaluate the next in order transaction request. If the next request can be partially or completely retired by the memory read access previously started, then the memory access that would have been normally required may be skipped and the data from the previous memory read access is used instead. This AGP read transaction merging may continue until the next in order transaction read request is located in a different cacheline of memory or the original memory request is ready to return data. A memory data buffer may also be utilized to store unused quadwords of the cacheline read from a memory access so that some subsequent AGP transaction requests may be retired without having to access a previously read cacheline of memory.

Claims

1. A computer system having a core logic chipset which connects a computer processor and memory to an accelerated graphics port (AGP) processor, said system comprising:

a processor executing software instructions and generating graphics data;

a main memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of said plurality of bytes of storage has a unique address;

said software instructions and said graphics data being stored in some of said plurality of bytes of storage of said main memory;

an accelerated graphics port (AGP) processor generating video display data from said graphics data and adapted for connection to a video monitor to display said video display data;

a core logic chipset comprising a processor interface logic, a memory interface logic and an AGP interface logic;

said processor interface logic is connected to said processor;

said memory interface logic is connected to said main memory;

said processor interface logic is connected to said memory interface logic;

said AGP interface logic is connected to said memory interface logic;

said AGP interface logic having an AGP request queue that stores transaction requests from said AGP processor, wherein a read request in said AGP request queue causes said memory interface logic to initiate a cacheline read access of said main memory to retire the read request; and

said AGP interface logic reading a next transaction request from said AGP request queue to determine if the initiated cacheline read access of said main memory can retire the next transaction request, if so, the next transaction request does not cause said memory interface logic to initiate another cacheline access of said main memory, and if not so, the next transaction request causes said memory interface logic to initiate another cacheline access of said main memory.

2. The computer system of claim 1, wherein said AGP interface logic continues to read subsequent transaction requests from said AGP request queue to determine if the initiated cacheline read access of said main memory can retire these subsequent transaction requests, if so, the subsequent transaction requests do not cause said memory interface logic to initiate another cacheline access of said main memory, and if not so, a one of the subsequent transaction requests which cannot be retired from the initiated cacheline read access will cause said memory interface logic to initiate a subsequent cacheline access of said main memory.

3. The computer system of claim 1, wherein said AGP logic further comprises a memory data buffer for storing bytes of data received from the initiated cacheline read access of said main memory, and said AGP logic using these stored bytes of data in said memory data buffer to retire a future AGP transaction read request.

4. The computer system of claim 3, wherein said memory data buffer stores bytes of data from a plurality of cacheline read accesses of said main memory.

5. The computer system of claim 4, wherein the plurality of cacheline read accesses of said main memory are the initiated cacheline read access and at least one prefetched cacheline read access of said main memory.

6. The computer system of claim 4, wherein the bytes of data stored in said memory data buffer are used to retire at least one future AGP transaction read request.

7. The computer system of claim 3, wherein the future AGP transaction read request is a plurality of future AGP transaction read requests.

8. The computer system of claim 1, wherein the transaction read request from said AGP processor is for at least one quadword, where a quadword is eight bytes of data.

9. The computer system of claim 8, wherein a cacheline is four quadwords.

10. The computer system of claim 1, wherein said core logic chipset further comprises:

a peripheral component interconnect (PCI) interface logic connected to PCI input-output devices on a PCI bus; and

said PCI interface logic connected to said processor interface logic and said memory interface logic.

11. The computer system of claim 1, further comprising a PCI-to-PCI bridge connected between said PCI bus and said AGP processor.

12. The computer system of claim 1, further comprising a plurality of processors.

13. The computer system of claim 1, further comprising a video display.

14. The computer system of claim 1, further comprising a network interface card, a hard disk, a floppy disk drive, a modem, a keyboard, and a mouse.

15. The computer system of claim 1, further comprising a serial port, a parallel port, a keyboard and a real time clock.

16. The computer system of claim 1, further comprising a read only memory basic input-output system (ROM BIOS), a non-volatile random access memory (NVRAM), a tape drive and a CD ROM drive.

17. A method, in a computer system having a core logic chipset which connects a computer processor and main memory to an accelerated graphics port (AGP) processor, of merging AGP transaction read requests from the AGP processor into a cacheline of main memory access, said method comprising the steps of:

a) reading an accelerated graphics port (AGP) transaction request from an AGP request queue;

b) if the AGP transaction request is a read request then start a read access to the computer system main memory for a cacheline of AGP graphics data for retiring the AGP transaction read request;

c) reading a next AGP transaction request from the AGP request queue to determine if the next AGP transaction request can be retired from the cacheline of AGP graphics data being accessed from the main memory;

d) if the next AGP transaction request is a read request and can be retired from the cacheline of AGP graphics data being accessed then read another AGP transaction request from the AGP request queue;

e) if the next AGP transaction request is a read request but cannot be retired from the cacheline of AGP graphics data being accessed then start another access to the computer system main memory for another cacheline of AGP graphics data for retiring the next AGP read request; and

f) repeating steps c) through e) until there are no more AGP transaction requests in the AGP request queue.

18. The method of claim 17, further comprising the step of storing the cacheline of AGP graphics data in a memory data buffer for retiring a future AGP transaction read request.

19. The method of claim 17, further comprising the step of prefetching another cacheline of AGP graphics data and storing the another cacheline of AGP graphics data in a memory data buffer for retiring at least one future AGP transaction read request.

20. The method of claim 19, wherein the step of prefetching another cacheline of AGP graphics data is the step of prefetching a plurality of cachelines of AGP graphics data from the main memory.

21. The method of claim 20, further comprising the step of storing the prefetched plurality of cachelines of AGP graphics data in a memory data buffer for retiring future AGP transaction read requests.

22. The method of claim 17, further comprising the step of setting a bit corresponding to each AGP transaction request in the AGP request queue that can be retired by the cacheline of AGP graphics data being accessed so that a grant signal and target ready signal will be sent to the AGP processor when the cacheline of AGP graphics data is read from the main memory read access.

23. A core logic chipset adapted for connecting a computer processor and memory to an accelerated graphics port (AGP) processor, comprising:

an accelerated graphics port (AGP) request queue;

an AGP data and control logic;

an AGP arbiter;

a memory interface and control logic adapted for connection to a main memory; and

a processor interface adapted for connection to at least one processor;

wherein,

said AGP request queue is connected to said memory interface and control logic;

said AGP data and control logic is connected to said memory interface and control logic;

said AGP data and control logic is adapted for connection to an AGP bus having an AGP device;

wherein,

said AGP request queue stores AGP transaction requests for the AGP device;

said AGP data and control logic reads an AGP transaction request from said AGP request queue and if the AGP transaction request is a read request then said memory interface and control logic initiates a read access of a cacheline of main memory so as to retire the read request; and

said AGP data and control logic reads a next AGP transaction request from said AGP request queue to determine if the initiated read access of the cacheline of main memory can retire the next AGP transaction request, if so, the next AGP transaction request does not cause said memory interface and control logic to initiate read access of another cacheline of the main memory, and if not, the next AGP transaction request causes said memory interface and control logic to initiate a read access of another cacheline of the main memory.

24. The core logic chipset of claim 23, further comprising a memory data buffer for storing the accessed cacheline of main memory, the stored cacheline of main memory being used to retire at least one future AGP transaction read request.

25. The core logic chipset of claim 24, wherein said memory data buffer can store a plurality of cachelines of main memory.