×

Accelerated graphics port read transaction merging

  • US 5,986,677 A
  • Filed: 09/30/1997
  • Issued: 11/16/1999
  • Est. Priority Date: 09/30/1997
  • Status: Expired due to Term
First Claim
Patent Images

1. A computer system having a core logic chipset which connects a computer processor and memory to an accelerated graphics port (AGP) processor, said system comprising:

  • a processor executing software instructions and generating graphics data;

    a main memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of said plurality of bytes of storage has a unique address;

    said software instructions and said graphics data being stored in some of said plurality of bytes of storage of said main memory;

    an accelerated graphics port (AGP) processor generating video display data from said graphics data and adapted for connection to a video monitor to display said video display data;

    a core logic chipset comprising a processor interface logic, a memory interface logic and an AGP interface logic;

    said processor interface logic is connected to said processor;

    said memory interface logic is connected to said main memory;

    said processor interface logic is connected to said memory interface logic;

    said AGP interface logic is connected to said memory interface logic;

    said AGP interface logic having an AGP request queue that stores transaction requests from said AGP processor, wherein a read request in said AGP request queue causes said memory interface logic to initiate a cacheline read access of said main memory to retire the read request; and

    said AGP interface logic reading a next transaction request from said AGP request queue to determine if the initiated cacheline read access of said main memory can retire the next transaction request, if so, the next transaction request does not cause said memory interface logic to initiate another cacheline access of said main memory, and if not so, the next transaction request causes said memory interface logic to initiate another cacheline access of said main memory.

View all claims
  • 4 Assignments
Timeline View
Assignment View
    ×
    ×