Data communication for memory

• US 5,986,948 A
• Filed: 09/23/1998
• Issued: 11/16/1999
• Est. Priority Date: 08/30/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Cloud, Eugene H.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lam, David
• Application Number:
  US09/159,118
• Time in Patent Office: 419 Days
• Field of Search: 365/193, 365/189.05, 365/189.08, 365/189.11, 365/189.01
• US Class Current: 365/193
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A memory circuit is described which has an output data strobe signal that indicates when valid data is available on the output lines. Several alternate signals and circuits are described which can be used for the output strobe signal. An echo clock signal is described which selectively follows an input clock signal in a synchronous memory system and indicated when valid output data is available. The output strobe signal is used to speed the reading of data from the output line by allowing a microprocessor, or other external circuit, to read the data from the output lines as soon as it is valid, thereby eliminating the need to wait a specified period of time.

Claims

1. A memory module comprising:

a plurality of synchronous memories;

a trigger circuit configured to receive a clock input signal on a clock signal input, the trigger circuit having an output for providing a pulsed signal which is generated in response to the clock input signal, the pulsed signal being delayed from the clock input signal and associated with data output from the memory module, and

an output driver circuit adapted to receive the pulsed signal and provide an output data strobe signal indicating when valid data is available from the memory module on data communication lines.

2. The memory module of claim 1 wherein the output data strobe signal is synchronized with the start of the output data from the integrated circuit memory device.

3. The memory module of claim 2 wherein the output data strobe signal is inhibited during non-read memory operations.

4. The memory module of claim 1 wherein the output data strobe signal is out of phase with the start of the output data from the integrated circuit memory device, such that a transition of the pulsed signal occurs during the output of data.

5. The memory module of claim 4 wherein the output data strobe signal is inhibited during non-read memory operations.

6. The memory module of claim 1 wherein the output data strobe signal has a frequency which is n-times a frequency of the clock input signal.

7. The memory module of claim 6 wherein the output data strobe signal is inhibited during non-read memory operations.

8. The memory module of claim 6 wherein the output data strobe signal is out of phase with the start of the output data from the integrated circuit memory device, such that a transition of the pulsed signal occurs during the output of data.

9. The memory module of claim 6 wherein the output data strobe signal has a frequency which is two-times a frequency of the clock input signal.

10. The memory module of claim 6 wherein both rising and falling edges of the output data strobe signal are synchronized with the start of the output data from the integrated circuit memory device.

11. The memory module of claim 6 wherein the output data strobe signal is inhibited during non-read memory operations.

12. The memory module of claim 1 wherein both rising and falling edges of the output data strobe signal are synchronized with the start of the output data from the integrated circuit memory device.

13. The memory module of claim 1 wherein the output data strobe signal is inhibited during non-read memory operations.

14. A memory module comprising:

a plurality of synchronous memories;

a trigger circuit configured to receive a clock input signal on a clock signal input, the trigger circuit having an output for providing a pulsed signal which is generated in response to the clock input signal, the pulsed signal being delayed from the clock input signal and associated with data output from the memory module; and

an output driver circuit adapted to receive the pulsed signal and provide a plurality of output data strobe signals indicating when valid data is available from the memory module on data communication lines, each one of the plurality of output data strobe signals corresponding with a byte of data.

15. The memory module of claim 14 wherein the output data strobe signal is synchronized with the start of the output data from the integrated circuit memory device.

16. The memory module of claim 15 wherein the output data strobe signal is inhibited during non-read memory operations.

17. The memory module of claim 14 wherein the output data strobe signal is out of phase with the start of the output data from the integrated circuit memory device, such that a transition of the pulsed signal occurs during the output of data.

18. The memory module of claim 17 wherein the output data strobe signal is inhibited during non-read memory operations.

19. The memory module of claim 14 wherein the output data strobe signal has a frequency which is n-times a frequency of the clock input signal.

20. The memory module of claim 19 wherein the output data strobe signal is inhibited during non-read memory operations.

21. The memory module of claim 19 wherein the output data strobe signal is out of phase with the start of the output data from the integrated circuit memory device, such that a transition of the pulsed signal occurs during the output of data.

22. The memory module of claim 19 wherein the output data strobe signal has a frequency which is two-times a frequency of the clock input signal.

23. The memory module of claim 19 wherein both rising and falling edges of the output data strobe signal are synchronized with the start of the output data from the integrated circuit memory device.

24. The memory module of claim 19 wherein the output data strobe signal is inhibited during non-read memory operations.

25. The memory module of claim 14 wherein both rising and falling edges of the output data strobe signal are synchronized with the start of the output data from the integrated circuit memory device.

26. The memory module of claim 14 wherein the output data strobe signal is inhibited during non-read memory operations.

27. A synchronous memory device comprising:

an input for receiving a clock signal;

an output for providing a plurality of echo clock signals which substantially follows the clock signal during a data read operation, transitions of the echo clock signal indicate when data is available on data output lines, each one of the plurality of the echo clock signals corresponding with a byte of output data; and

a generating circuit for producing the echo clock signals.

28. The synchronous memory device of claim 27 wherein the echo clock signals also substantially follow the clock signal during non-data read operations.

29. The synchronous memory device of claim 27 wherein either a rising or falling transition of the echo clock signals indicate that data is available on the data output lines.

30. The synchronous memory device of claim 27 wherein the echo clock signals indicate a start of data transmission on the data output lines.

31. A method of outputting data from a synchronous memory device, the method comprising:

receiving a clock input signal with the synchronous memory device;

initiating a memory read operation;

generating an echo clock signal which substantially follows the clock signal during the memory read operation; and

outputting the echo clock signal from the synchronous memory data, the echo clock signal corresponds to output data from the synchronous memory device.

32. The method of claim 31, wherein the echo clock signal is synchronized with data output from the synchronous memory device so that a transition of the echo clock signal corresponds to a start of the data output.

33. The method of claim 31 wherein a transition of the echo clock is ninety (90) degrees out-of-phase with a start of the data output.

34. The method of claim 31 wherein the output of the echo clock signal is inhibited during non-read operations.

35. The method of claim 31 wherein both rising and falling transitions of the echo clock signal are synchronized with data output from the synchronous memory device.

36. A method of outputting data from a synchronous memory device, the method comprising:

receiving a clock input signal with the synchronous memory device;

initiating a memory read operation;

generating a plurality of echo clock signals which substantially follows the clock signal during the memory read operation; and

outputting the echo clock signals from the synchronous memory data, each one of the echo clock signals correspond to a byte of output data from the synchronous memory device.

37. The method of claim 36 wherein the echo clock signals are synchronized with data output from the synchronous memory device so that a transition of the echo clock signals correspond to a start of the data output.

38. The method of claim 36 wherein a transition of the echo clock signals are ninety (90) degrees out-of-phase with a start of the data output.

39. The method of claim 36 wherein the output of the echo clock signals are inhibited during non-read operations.

40. The method of claim 36 wherein both rising and falling transitions of the echo clock signals are synchronized with data output from the synchronous memory device.