System and method for providing FDD and TDD modes of operation for a wireless communications device

• US 5,987,010 A
• Filed: 05/15/1997
• Issued: 11/16/1999
• Est. Priority Date: 05/15/1997
• Status: Expired due to Term

• Current Assignee: Microsemi Semiconductor (U.S.) Inc. (Microchip Technology Incorporated)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Schnizlein, Paul G.
• Primary Examiner(s): Ton, Dang
• Assistant Examiner(s): Sam, Phirin
• Application Number:
  US08/856,541
• Time in Patent Office: 915 Days
• Field of Search: 370/307, 370/276, 370/277, 370/279, 370/280, 370/281, 370/293, 370/294, 370/295, 370/335, 370/342, 370/310, 370/282, 455/78, 455/101, 455/133, 455/20, 455/93, 455/112, 455/113, 455/118, 455/553
• US Class Current: 370/280
• CPC Class Codes: H03K 2005/00247 using counters
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation

Abstract

A system and method is described herein for providing FDD and TDD modes of operation for a wireless communications device. The system includes a clock signal for FDD mode operation, a separate clock signal for TDD mode operation, where the TDD mode clock is twice the frequency of the FDD clock. Additionally, a counter is provided for counting bit times during a transmission or receive frame. The clock counter is reloaded after a pre-specified count is achieved. The pre-specified count is twice as great in TDD mode operation than in FDD mode operation to account for the fact that the bit periods are twice as long in FDD operation than during TDD operation since transmit and receive are at different frequencies and are not sharing the same channel.

Claims

1. A method of operating in both an FDD mode and a TDD mode for a wireless digital communications device, comprising the steps of:

a) providing a first clock signal for FDD mode operation;

b) providing a second clock signal for TDD mode operation;

c) providing a clock counter;

d) selecting between said first clock signal and said second clock signal to be input to said clock counter, wherein for FDD operation said first clock signal is input to said clock counter and for TDD operation said second clock signal is input to said clock counter; and

e) reloading said clock counter to a predetermined count value after a pre-specified-count is achieved by said clock counter, the pre-specified count value depending upon one of FDD operation and TDD operation.

2. The method of claim 1, wherein said clock counter comprises a transmit counter and a receive counter.

3. The method of claim 1, wherein said step of reloading is accomplished after said clock counter achieves a count of 72.

4. The method of claim 1, wherein said step of reloading is accomplished after said clock counter achieves a count of 144.

5. The method of claim 1, wherein said pre-specified count corresponds with a frame rate for a wireless digital communications device.

6. The method of claim 1, wherein said step of providing a first clock signal is accomplished by selecting between a fixed clock signal and a recovered clock signal.

7. The method of claim 6, wherein said fixed clock signal and said recovered clock signal are both at a first frequency for FDD mode operation and are both at a second frequency for TDD mode operation.

8. The method of claim 1, wherein said second clock signal has a rate twice that of said first clock signal.

9. The method as recited in claim 1 wherein said predetermined count value is zero.

10. A system for implementing FDD and TDD modes of operation for a wireless digital communications device, comprising:

a) a first clock signal generator which generates an FDD mode clock signal;

b) a second clock signal generator which generates a TDD mode clock signal;

c) a clock counter;

d) a selector device which selects between an output from said first clock signal generator and said second clock signal generator for input to said clock counter according to whether the system is operating in FDD or TDD mode;

wherein said clock counter is reloaded to a predetermined count value after said clock counter achieves a first pre-specified count for FDD mode of operations, and a second pre-specified count for TDD mode of operation.

11. The system of claim 10, wherein said FDD mode clock signal has a rate one half that of said TDD mode clock signal.

12. The system of claim 10, wherein said second pre-specified count is twice that of said first pre-specified count.

13. The system of claim 10, wherein said first count and said second count each correspond to a frame rate for a wireless digital communications device.

14. The system of claim 10, wherein said clock counter comprises a transmit counter and a receive counter.

15. The system of claim 10, wherein said first clock signal generator generates said FDD mode clock signal by selecting between a fixed clock signal and a recovered clock signal.

16. The system of claim 10, wherein said second clock signal generator generates said TDD mode clock signal by selecting between a fixed clock signal and a recovered clock signal.

17. The system as recited in claim 10 wherein said predetermined count value is zero.

18. A system for implementing FDD and TDD modes of operation for a wireless digital communications device, comprising:

a base clock signal generator;

a first division circuit coupled to the base clock signal generator, the first division circuit operable to generate an FDD clock signal from a base clock signal generated by the base clock signal generator;

a second division circuit coupled to the base clock signal generator, the second division circuit operable to generate a TDD clock signal from the base clock signal;

a selector coupled to the first and second division circuits, the selector operable to receive a mode select signal, the selector selecting between the FDD clock signal and the TDD clock signal according to the mode select signal;

a counter coupled to the selector; and

a decode circuit coupled to the counter, the decode circuit operable to receive a counter signal from the counter and to provide a reload signal to the counter, the reload signal causing the counter to return to a predetermined value.

19. The system of claim 18 wherein the decode circuit is operable to receive the mode select signal, the decode circuit providing the reload signal according to the mode select signal.

20. The system of claim 18 wherein the decode circuit is operable to receive a clock signal selected by the selector, the decode circuit providing the reload signal according to the clock signal.