Method of synchronizing signals and a device herefor

• US 5,987,080 A
• Filed: 03/26/1997
• Issued: 11/16/1999
• Est. Priority Date: 10/03/1994
• Status: Expired due to Term

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Berghager, Hans Arne Peter, Johansson, Bjorn Inge, Sissonen, Raimo Kalevi
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): Webster, Bryan
• Application Number:
  US08/809,635
• Time in Patent Office: 965 Days
• Field of Search: 375/354, 375/363, 375/364, 341/173, 341/178, 377/33, 370/473, 370/474, 370/476, 370/503, 370/509, 370/505, 370/512, 370/520, 370/523
• US Class Current: 375/354
• CPC Class Codes: H04L 2012/5674 Synchronisation, timing recovery or alignment
• CPC Class Codes: H04L 7/044 using a single bit, e.g. start stop bit
• CPC Class Codes: H04L 7/08 the synchronisation signals recurring cyclically
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

The present invention relates to a synchronization method and to a system for establishing in a signal receiving unit (4) a time position of a significant bit position occurring among received information-carrying bit positions (40a, 40b) into which a predetermined number of uniformly distributed line-code related bit positions are inserted.

Claims

1. A method of synchronizing a signal transfer system, comprising a signal transmitting unit for transmitting digitalized information-carrying signals, a signal transfer medium and a signal receiving unit for receiving said transmitted digitalized information-carrying signals, by establishing, in the receiving unit, a time position in which a significant bit position occurs among received information-carrying digitalized signals, the method comprising the steps of:

mutually coupling a number of 1-bit registers belonging to the receiving unit to form a ring-coupled shift register, wherein said 1-bit registers are initially allocated digital values which correspond to the digital value of a chosen and transmitted line code, said number of 1-bit registers corresponding to a chosen number of bit positions in each subsection;

comparing a stream of bit positions and their respective digital values which can be comprehended by the receiving unit with the relevant digital value stored in a resettable 1-bit register; and

setting the 1-bit register to a differing value by a bit-position having a digital value that differs from a line-code value, the differing value being the digital value wherein, when only one 1-bit register presents a digital value that corresponds to the digital value of the line code, the digital value represents the value of the line-code time position,

wherein the signal transmitting unit is adapted to transmit digital information having predetermined bit positions and coordinated to form data packets in the form of sequential bit positions and to transmit data packets on data packets, a predetermined number of uniformly distributed line-code related bit positions being inserted in the bit positions of each data packet with a predetermined number of information-carrying bit positions between mutually adjacent line-code related bit positions, and

the signal receiving unit is adapted to receive inserted line-code related bit positions which are coordinated to data packets and which contain digital information, the receiving unit including first means for establishing the time positions of a number of line-code related significant bit positions, the information-carrying and line-code related bit positions received in the signal receiving divisible into a number of equal subsections with a predetermined number of the subsections forming a complete data packet with inserted line-code related bit positions, and the line-code related bit positions are each allocated one and the same significant digital value.

2. The method of claim 1 further comprising:

reading the values of the bit positions in said shift register with the aid of a control circuit; and

evaluating the lone time position that has the same value as the line code.

3. The method of claim 1, further comprising:

activating a synchronizing unit with the aid of said control circuit; and

giving a synchronizing time position related to the line code position, wherein said control circuit activates means for eliminating the line code positions.

4. The method of claim 1, further comprising:

periodically introducing a line-code related bit position into transmitter information-carrying signals with the aid of a signal transmitting unit, with said line-code related bit positions having mutually the same digital values.

9. A method according to claim 2, further comprising:

activating a synchronizing unit with the aid of said control circuit; and

giving a synchronizing time position related to the line code position, wherein said control circuit activates means for removing the line code positions.

10. A method according to claim 2, further comprising:

periodically introducing a line-code related bit position into transmitter information-carrying signals with the aid of a signal transmitting unit, said line-code related bit positions having mutually the same digital values.

11. A method according to claim 3, further comprising:

periodically introducing a line-code related bit position into transmitter information-carrying signals with the aid of a signal transmitting unit, said line-code related bit positions having mutually the same digital values.

12. A method according to claim 9, further comprising:

periodically introducing a line-code related bit position into transmitter information-carrying signals with the aid of a signal transmitting unit, said line-code related bit positions having mutually the same digital values.

5. A system for establishing a time position in a signal receiving unit, the time position being represented by a periodic occurrence among received information carrying bit positions of a significant bit position having a specific digital representation of a line code, said system comprising:

a means having a number of 1-bit registers that are initially allocated digital values which correspond to the digital value of said significant bit position, wherein the number of 1-bit registers corresponds to the number of bit positions in a subsection of a data packet provided with a line code and the 1-bit registers are ring-coupled to form a shift register;

a comparing means for comparing the digital value of each occurring bit position with a digital value in an re-settable 1-bit register; and

changing means for changing the digital value of a 1-bit register whenever the digital value of a bit position differs from the value initially inserted wherein when only one register in the ring-coupled 1-bit registers exhibits the initially inserted digital value, this bit position is taken to constitute the line-code time position.

6. A system according to claim 5 further comprising a control circuit for reading the digital value of each 1-bit register.

7. A system according to claim 6, wherein said control circuit activates a synchronizing unit.

8. A system according to claim 5, wherein said control circuit activates a circuit for removing line-code bit positions.