Power management masked clock circuitry, systems and methods
First Claim
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1. An electronic system comprising:
- a register for duty cycle data; and
a clock circuit coupled to said register, said clock circuit comprising first circuitry and second circuitry wherein said first circuitry provides a first circuitry signal and said second circuitry combines said duty cycle data and said first circuitry signal into a second circuitry signal having a duty cycle defined by said duty cycle data and a frequency defined by said first circuitry signal.
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Abstract
An electronic system (100) includes a register (TONTOFF) for data and a clock circuit (2340, 708) coupled to the register and responsive to the data in the register to generate a series of clock pulses (CPU-- CLK). The series of clock pulses occupies time intervals (2550) interspersed with time intervals free of clock pulses (2552), as an output having a ratio of the time intervals responsive to the data. Other devices, systems and methods are also disclosed.
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Citations
36 Claims
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1. An electronic system comprising:
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a register for duty cycle data; and a clock circuit coupled to said register, said clock circuit comprising first circuitry and second circuitry wherein said first circuitry provides a first circuitry signal and said second circuitry combines said duty cycle data and said first circuitry signal into a second circuitry signal having a duty cycle defined by said duty cycle data and a frequency defined by said first circuitry signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An electronic device comprising:
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a register for duty cycle data; a clock circuit, coupled to said register, comprising first circuitry and second circuitry wherein said first circuitry provides a first circuitry signal and said second circuitry combines said duty cycle data and said first circuitry signal into a second circuitry signal having a duty cycle defined by said duty cycle data and a frequency defined by said first circuitry signal. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. An integrated circuit comprising:
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a power management circuit having an output representing the presence or absence of a standby state; a register for duty cycle data; a counter having a multi-bit output; a control circuit, coupled to said register and said counter, responsive to the data in said register to repeatedly generate pulses having a duty cycle and a frequency, said duty cycle responsive to said duty cycle data and said frequency responsive to said counter output, said control circuit including a comparator having a first multibit input coupled to receive said duty cycle data from said register and a second multibit input coupled to receive said multi-bit output of said counter; and a logic circuit coupled to the output of said power management circuit to produce a single logic level when the output of the power management circuit represents that the standby state is absent, and to pass the pulses from said control circuit to an output terminal when the output of the power management circuit represents that the standby state is present.
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29. An integrated circuit comprising:
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a system management interrupt (SMI) circuit having a periodic SMI signal source and providing a periodic SMI control signal representing the presence or absence of the periodic SMI signal from said source; a register for mask clock data; a counter having a multi-bit output; a control circuit responsive to said mask clock data to repeatedly generate pauses having a duty cycle and a frequency, said duty cycle responsive to said mask clock data and said frequency responsive to said counter output, said control circuit including a comparator having a first multibit input coupled to receive said mask clock data and a second multibit input coupled to receive said multi-bit output of said counter, said control circuit further responsive to said periodic SMI control signal to gate either the periodic SMI source or a predetermined clock to said counter depending on the state of said periodic SMI control signal.
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30. A computer system comprising:
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a first integrated circuit chip comprising; a microprocessor device; and a modulating circuit for modulating a clock signal with a digital masking signal to produce a series of clock pulses interspersed with intervals free of clock pulses to said microprocessor, and a second integrated circuit chip comprising; a power management circuit having an output representing the presence or absence of a standby state; a register for data; a counter having a multi-bit output; a control circuit responsive to the data in said register to repeatedly generate pulses of said digital masking signal having a duty cycle, said duty cycle responsive to the data in the register, said control circuit including a comparator having a first multibit input coupled to receive the data from said register and a second multibit input coupled to receive the multi-bit output of said counter, the comparator providing as an output the pulses of said digital masking signal; and a logic circuit coupled to the output of said power management circuit to produce a single logic level when the output of the power management circuit represents that the standby state is absent, and to pass the pulses of the digital masking signal from said control circuit to an output coupled to said modulating circuit in the first integrated circuit when the output of the power management circuit represents that the standby state is present. - View Dependent Claims (31)
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32. A method of operating a computer system having a microprocessor device and a clock circuit, comprising:
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steering data in a register; generating an output of a counter having a selected frequency; comparing said data in said register to sad output of said counter; and generating pulses having a duty cycle and a frequency, said duty cycle responsive to said data and said frequency responsive to said counter output. - View Dependent Claims (33, 34, 35, 36)
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Specification