Register reservation method for fast context switching in microprocessors

• US 5,987,258 A
• Filed: 06/27/1997
• Issued: 11/16/1999
• Est. Priority Date: 06/27/1997
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Gupta, Anil, Daniel, Thomas
• Primary Examiner(s): Hafiz, Tariq R.
• Assistant Examiner(s): Chaki, Kakali
• Application Number:
  US08/883,137
• Time in Patent Office: 872 Days
• Field of Search: 395/705, 395/706, 395/707, 395/708, 395/709, 395/733, 395/735, 395/736, 395/678, 709/107, 709/108, 712/228, 710/260, 710/262, 710/263, 710/266, 710/269
• US Class Current: 717/124
• CPC Class Codes: G06F 9/462 with multiple register sets

Abstract

Microprocessor main programs and their interrupt handling routines are written in a high level programming language such as C. Each is compiled separately, and each is compiled invoking a compiler option which commands the compiler to not use a given set of registers in the compiled code. Post-processing is then performed on the compiled interrupt code to replace accesses to a first set of registers with accesses to the given set of registers. The result is that while both the main program and the interrupt handler were written in C, the compiled code for each employs different registers. This allows context switching from the main program to the interrupt handler and back again with almost none of the overhead traditionally associated with context switching register save and restore operations during exception handling.

Claims

1. A method of decreasing interrupt handling overhead time in a processor-based system by eliminating context save and context restore operations associated with interrupt handler routines, the system including a processor, the processor having a first register set and a second register set, the method comprising the steps of:

(a) providing an interrupt handler in a high level programming language;

(b) providing a main program in the high level programming language;

(c) compiling the interrupt handler into interrupt handler assembly code;

(d) post-processing the interrupt handler assembly code by replacing accesses to the first register set with accesses to the second register set;

(e) compiling the interrupt handler assembly code into interrupt handler object code;

(e) compiling the main program into main program object code, the main program compiling step including the substep of invoking a compiler option which commands the compiler not to use the second register set; and

(f) linking the post-processed interrupt handler object code and the main program object code.

2. The method of claim 1 wherein:

the interrupt handler object code does not perform context save and context restore operations.

3. The method of claim 1 wherein:

the main program object code does not store critical information in registers within the second register when the interrupt handler is enabled.

4. The method of claim 3 wherein:

the main program object codes does not store any information within registers within the second register set.

5. A method of decreasing exception handling overhead time in a processor-based system by eliminating context save and context restore operations, the system including a processor having registers comprising a first register set and a second register set, the method comprising the steps of:

(a) providing an exception routine in a high level programming language;

(b) processing said exception routine to executable exception code such that said executable exception code is prevented from employing registers from the first register set and is permitted to employ registers from the second register set, the executable exception code not performing a context save and a context restore with respect to all of the registers; and

(c) providing a main executable program, the main executable program not storing critical data in registers from the second register set when said exception routine is enabled.

6. The method of claim 5 wherein:

the executable exception code does not perform a context save and context restore with respect to any registers.

7. The method of claim 6 wherein step (c) further comprises the substeps of:

(c1) providing a main program source code in a high level assembly language; and

(c2) commanding a compiler to compile said main program source code to main program executable code such that said main program executable code is prevented from employing registers from the second register set when the exception routine is enabled.

8. The method of claim 5 wherein step (b) comprises the substeps of:

(b1) commanding a compiler to compile said exception routine to executable exception code such that said executable exception code is prevented from employing registers from the second register set; and

(b2) post-processing said executable exception code by replacing accesses to said first register set with accesses to said second register set.

9. The method of claim 8 wherein:

the executable exception code in substeps (b1) and (b2) is interrupt assembly code; and

wherein step (b) further comprises the substep of;

(b3) compiling said interrupt assembly code to interrupt object code.

10. The method of claim 5 wherein step (b) comprises the step of:

commanding a compiler to compile said exception routine to executable exception code such that said executable exception code is prevented from employing registers from the first register set.

11. The method of claim 10 wherein step (c) comprises the substeps of:

(c1) providing a main program source code;

(c2) compiling said main program source code to main program executable code such that said main program executable code is prevented from employing registers from the second register set.

12. The method of claim 11 wherein substep (c2) comprises the step of:

commanding a register reserve option when compiling the main program source code.

13. The method of claim 5 further comprising the step of

(d) executing the main executable program in conjunction with said executable exception code.

14. A machine readable memory containing executable code produced according to the method of claim 5.

15. An electronic processing system comprising:

a processor;

the machine readable memory according to claim 14; and

an interrupt source for causing said executable exception code to be invoked.

16. A read only memory containing executable code produced according to the method of claim 5.

17. A random access memory containing executable code produced according to the method of claim 5.

18. An electronic system for preparing and executing a processor program which executes interrupt routines and main program at substantially reduced context switching times, the system comprising:

a compiler for compiling a source interrupt routine to a compiled interrupt routine;

means for post-processing the compiled interrupt routine to prevent the compiled interrupt routine from writing data into registers within a first register set; and

means for compiling a source main program such that a resulting compiled main program employs registers from the first register set and does not employ registers from a second register set at an interrupt enabled portion of said compiled main program; and

means for executing together said compiled main program and said compiled interrupt routine.

19. The system of claim 18 wherein said post-processing means comprises:

means for replacing accesses to the first register set with accesses to a second register set.