Offset-compensated linear RF detector having a detector part and a linearizer part

• US 5,987,312 A
• Filed: 02/13/1997
• Issued: 11/16/1999
• Est. Priority Date: 04/05/1995
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Nokia Telecommunications Oy (Nokia Corporation)
• Inventors: Dekker, Andre P.
• Primary Examiner(s): Urban, Edward F.
• Assistant Examiner(s): Gesesse, Tilahun
• Application Number:
  US08/750,324
• Time in Patent Office: 1,006 Days
• Field of Search: 455/115, 455/126, 455/127, 455/226.1, 455/226.2, 330/260, 330/259, 330/291
• US Class Current: 455/115.1
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 3/45479 characterised by the way of common mode signal rejection

Abstract

A base station receiver and a reception method in a CDMA cellular radio system includes, in each cell, at least one base station communicating with a plurality of mobile stations situated within its area. The base stations measure the direction angle of a signal arriving from each mobile station with respect to the base station, and communicate with the mobile stations using antenna beams that change in time. The angles of the greatest gain of the beams are adjusted according to signal components arriving from the mobile station. In order to provide detection of good quality without a great deal of calculation, the detection of the desired signal utilizes simultaneously several signals received from different mobile stations taking into account the incoming direction of the signals when selecting the signals.

Claims

1. A linear RF detector, comprising:

a detector part having a detector diode biased with bias current, and a linearizer part having an operation amplifier having an inverting input to which is connected both the output of the detector part and a feedback path coming from the output of the operation amplifier;

said feedback path comprising a first transistor circuit in which the base of one transistor is grounded, the first transistor circuit being connected such that it generates a first offset voltage at the output of said operation amplifier, said first offset voltage being the sum of each transistor base-emitter voltage of the first transistor circuit;

the output of said operation amplifier being connected to a second transistor circuit for generating a second offset voltage, said second offset voltage being arranged to cancel said first offset voltage whereby the output offset voltage of said detector is substantially zero.

5. An RF detector according to claim 1, further comprising:

a second biasing voltage source connected to a non-inverting input of operation amplifier through a diode that is similar to said detector diode (D1a).

6. An RF detector according to claim 1, wherein:

said second transistor circuit is located in said feedback path.

7. An RF detector according to claim 1, wherein:

said second transistor circuit is connected in series with said operation amplifier.

8. An RF detector according to claim 7, wherein:

said second transistor circuit comprises two transistors which together from a super emitter follower.

2. A linear RF detector, comprising:

a detector part having a detector diode biased with bias current, and a linearizer part having an operation amplifier having an inverting input to which is connected both the output of the detector part and a feedback path coming from the output of the operation amplifier;

said feedback path comprising a first transistor circuit in which the base of one transistor is grounded, the first transistor circuit being connected such that it generates a first offset voltage at the output of said operation amplifier, said first offset voltage being the sum of each transistor base-emitter voltage of the first transistor circuit;

the output of said operation amplifier being connected to a second transistor circuit for generating a second offset voltage, said second offset voltage being arranged to cancel said first offset voltage whereby the output offset voltage of said detector is substantially zero;

wherein said first transistor circuit comprises a first transistor as said one transistor whose base is grounded, and a second transistor whose base is connected to the emitter of the first transistor and whose collector current flows in said feedback path.

4. An RF detector according to claim 2, wherein:

said second transistor circuit comprises a first transistor and a second transistor connected in a darlington configuration from the collector of which the output voltage of said detector is obtained, the emitter of the first transistor of said second transistor circuit being operationally connected to the output of said operation amplifier; and

said first and second transistor circuits are designed such that

space="preserve" listing-type="equation">I.sub.3a I.sub.b =I.sub.3b I.sub.2b

holds true, I_2b and I_3b being the collector currents of the transistors in said second transistor circuit, I_b being the bias current of said detector diode, and I_3a being the collector current of said first transistor in said first transistor circuit.

3. A linear RF detector, comprising:

a detector part having a detector diode biased with bias current, and a linearizer part having an operation amplifier having an inverting input to which is connected both the output of the detector part and a feedback path coming from the output of the operation amplifier;

said feedback path comprising a first transistor circuit in which the base of one transistor is grounded, the first transistor circuit being connected such that it generates a first offset voltage at the output of said operation amplifier, said first offset voltage being the sum of each transistor base-emitter voltage of the first transistor circuit;

the output of said operation amplifier being connected to a second transistor circuit for generating a second offset voltage, said second offset voltage being arranged to cancel said first offset voltage whereby the output offset voltage of said detector is substantially zero;

wherein said second transistor circuit comprises a first transistor and a second transistor connected in a darlington configuration from the collector of which the output voltage of said detector is obtained, the emitter of the first transistor of said second transistor circuit being operationally connected to the output of said operation amplifier.