Flash memory accessed using only the logical address

• US 5,987,563 A
• Filed: 12/10/1998
• Issued: 11/16/1999
• Est. Priority Date: 02/20/1992
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Itoh, Hiroyuki, Matsui, Noriyuki
• Primary Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US09/208,474
• Time in Patent Office: 341 Days
• Field of Search: 711/1, 711/103, 711/156, 711/203, 714/48
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written

Abstract

A flash memory control apparatus and method which enables updating of data at high speed. The flash memory control apparatus includes a flash memory having a memory region which is divided into a plurality of sectors each including a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data; and a control device, coupled to the flash memory, for making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector. The flash memory control method includes the steps of: (a) dividing a memory region of a flash memory into a plurality of sector; and (b) making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector. Each of the sectors includes a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data.

Claims

1. A method of controlling a non-volatile memory having a plurality of blocks, said memory being erased by a minimum unit of one block, said method comprising the steps of:

(a) dividing each of the blocks of the memory into a plurality of sectors, each of said sectors including a storage portion for storing at least a logical address of the sector, and a data part for storing data; and

(b) accessing a desired sector of the memory by specifying the logical address of the desired sector, comparing the specified logical address with said logical address stored in each of the sectors, and detecting a sector which has a logical address matching the specified logical address.

3. The method as claimed in claim 1, wherein a total memory region of the memory amounts to m blocks, m-1 blocks are used as an effective memory region, and the remaining one block is used as a work block.

4. The method as claimed in claim 3, which further comprises the steps of:

(c) adjusting data in the memory using the work block after a write operation with respect to all of the m-1 blocks ends.

5. The method as claimed in claim 1, wherein said step (a) divides the memory region so that each sector further includes an error detection data part for storing information which is used for detecting and correcting an error in the data stored in the data part.

6. The method as claimed in claim 1, wherein each of said sectors further includes an erasure managing part for storing information which indicates at least whether or not the sector may be erased, and said step (a) divides a memory region of the memory so that the erasure managing part of each sector includes an erasure enable flag which has an initial state if the data part of the sector to which said erasure enable flag belongs is valid and has a state other than the initial state if the data part of the sector to which said erasure enable flag belongs is invalid.

7. The method as claimed in claim 6, wherein the erasure managing part of each sector includes a plurality of erasure enable flags.

8. The method as claimed in claim 1, wherein each of said sectors further includes an erasure managing part for storing information which indicates at least whether or not the sector may be erased, and said step (a) divides a memory region of the memory so that the erasure managing part of each sector includes a defective sector flag which indicates whether or not the sector is defective.

9. The method as claimed in claim 8, wherein the erasure managing part of each sector includes a plurality of defective sector flags.

10. The method as claimed in claim 1, wherein each of said sectors further includes an erasure managing part for storing information which indicates at least whether or not the sector may be erased, and further comprising the steps of:

(c) managing empty sectors of the memory based on the information stored in the erasure managing part of each sector.

2. The method as claimed inclaim 1, wherein the memory is made up of at least one memory chip.

11. A non-volatile memory device which is erased by a minimum unit of one block, comprising:

a memory having a plurality of blocks, each of said blocks being divided into a plurality of sectors each including a storage portion for storing at least a logical address of the sector, and a data part for storing data; and

a control unit, coupled to said memory, accessing a desired sector of said memory by specifying a logical address of the desired sector, comparing the specified logical address with said logical address stored in each of the sectors, and detecting a sector which has a logical address matching the specified logical address.

12. The non-volatile memory device as claimed in claim 11, wherein said memory is made up of at least one memory chip.

13. The non-volatile memory device as claimed in claim 11, wherein a total memory region of said memory amounts to m blocks, m-1 blocks are used as an effective memory region, and the remaining one block forms a work block.

14. The non-volatile memory device as claimed in claim 13, wherein said control unit includes a part which adjusts data in said memory using the work block after a write operation with respect to all of the m-1 blocks ends.

15. The non-volatile memory device as claimed in claim 11, wherein each sector further includes an error detection data part for storing information which is used for detecting and correcting an error in the data stored in the data part.

16. The non-volatile memory device as claimed in claim 11, wherein each of said sectors further includes an erasure managing part for storing information which indicates at least whether or not the sector may be erased, and the erasure managing part of each sector includes an erasure enable flag which has an initial state if the data part of the sector to which said erasure enable flag belongs is valid and has a state other than the initial state if the data part of the sector to which said erasure enable flag belongs is invalid.

17. The non-volatile memory device as claimed in claim 16, wherein the erasure managing part of each sector includes a plurality of erasure enable flags.

18. The non-volatile memory device as claimed in claim 11, wherein each of said sectors further includes an erasure managing part for storing information which indicates at least whether or not the sector may be erased, and the erasure managing part of each sector includes a defective sector flag which indicates whether or not the sector is defective.

19. The non-volatile memory device as claimed in claim 18, wherein the erasure managing part of each sector includes a plurality of defective sector flags.

20. The non-volatile memory device as claimed in claim 11, wherein each of said sectors further includes an erasure managing part for storing information which indicates at least whether or not the sector may be erased, and said control unit includes a part which manages empty sectors of said memory based on the information stored in the erasure managing part of each sector.

21. A memory controller for controlling a memory device having a memory including a plurality of blocks, each of said blocks being divided into a plurality of sectors each including a storage portion for storing at least a logical address of the sector and a data part for storing data, said memory being erased by a minimum unit of one block, said memory controller comprising:

a control unit accessing a desired sector of the memory by specifying a logical address of the desired sector, comparing the specified logical address with said logical address stored in each of the sectors, and detecting a sector which has a logical address matching the specified logical address.