Memory apparatus and memory control method

• US 5,987,573 A
• Filed: 02/06/1997
• Issued: 11/16/1999
• Est. Priority Date: 02/06/1996
• Status: Expired due to Term

• Current Assignee: Tokyo Electron Device Limited (Tokyo Electron Limited)
• Original Assignee: Tokyo Electron Limited
• Inventors: Hiraka, Seiji
• Primary Examiner(s): Cabeca, John W.
• Assistant Examiner(s): Namazi, Mehdi
• Application Number:
  US08/796,751
• Time in Patent Office: 1,013 Days
• Field of Search: 711/156, 711/205, 395/800.34, 395/555, 365/185.33, 365/185.21
• US Class Current: 711/156
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory

Abstract

An empty block table is constructed by 64 words×8 bits and has 512 memory positions 000H(A0) to IFFH(A511) one-to-one corresponding to 512 blocks BL0 to BL511 within a flash memory FMi. Empty data [a] of 1 bit is stored to each memory position (Aj). This empty data has value "1" when a block BLj corresponding to this memory position (Aj) is in an empty state at present. The empty data also has value "0" when no block BLj corresponding to this memory position (Aj) is in the empty state at present (when data are included in this block).

Claims

1. A memory apparatus comprising:

a semiconductor memory having a memory area divided in a plurality of blocks for selectively storing data and batch-erasing data in units of a block; and

a control section connected to a host computer for controlling a read/write operation in accordance with a command therefrom and having a table memory which has a plurality of memory positions in one-to-one correspondence with the blocks of the semiconductor memory, and stores data indicating absence of data in a memory position thereof which corresponds to one of the blocks in which no data is stored,

wherein the control section includes means for designating the memory positions of the table memory by means of addresses allocated to the blocks of the semiconductor memory, respectively, and

the control section includes table search means for searching for "empty state"-indicative data stored in the memory positions of the table memory in a predetermined sequence and stopping a search operation in response to a first detection of the memory position corresponding to one of the blocks which is in an empty state, and pointer means for issuing address data for designating the one of the blocks which has been detected by the table searching means and is in the empty state.

2. The memory apparatus according to claim 1, wherein the control section includes first table update means for updating "empty state"-indicative data stored in one of the memory positions of the table memory which corresponds to the one of the blocks which is in an empty state and is designated by the address data from the pointer means, to "empty-state"-indicative data when new data is written in said one of the blocks.

3. The memory apparatus according to claim 1, wherein the control section includes second update means for updating data stored in one of the memory positions of the table memory which corresponds to one of the blocks of the semiconductor memory which is subjected to a batch erasing to "empty state"-indicative data, when any one of the blocks is batch-erased.

4. A memory apparatus according to claim 1, wherein said control section includes means for converting a logical address from the host computer into a physical address for the semiconductor memory.

5. A memory apparatus comprising:

a plurality of semiconductor memories each having a memory area divided into a plurality of blocks for selectively storing data and batch-erasing data in units of a block;

an empty block table administrating section having an address counter common to the semiconductor memories, a control logic circuit, a SRAM having parallel memory regions corresponding to the semiconductor memories, respectively, a plurality of empty registers, an encoder and a plurality of pointer registers, and wherein

each of the memory regions of the SRAM has an empty block table for registering at least one empty block of each of the semiconductor memories, and writes "empty state"-indicative data in the table when it receives write-in address data from the address counter, a writing control signal from the control logic circuit and "empty state"-indicative data from the data register.

6. The memory apparatus according to claim 5, wherein the "empty-state"-indicative data is read out from the table of each of the memory regions of the SRAM in response to the readout address data from the address counter and the readout control signal from the control logic circuit, and the encoders encode the "empty state"-indicative data read out from the memory regions of the SRAM at the same time into binary address codes, and the pointer registers each produce address data by synthesizing the address data from the address counter and a corresponding one of the binary address codes from the encoders.

7. The memory apparatus according to claim 6, wherein the control logic circuit loads high-order address data of a pointer which is held by each of the pointer registers in the address counter, reads out "empty state"-indicative data of one word from the empty block table by means of the address data, and updates the "empty state"-indicative data stored in a memory position within one word designated by low-order address data of the "empty state"-indicative data of the readout one word, to "non-empty state indicative data.

8. A memory apparatus according to claim 5, wherein said SRAM includes an address conversion table in which a logical address from a host computer corresponds to a physical address for the semiconductor memory.

9. A memory control method comprising the steps of:

preparing a semiconductor memory device connected to a host computer and executing a read/write operation in accordance with a command from the host computer;

providing a plurality of memory positions in a table memory, the memory positions corresponding to a plurality of blocks obtained by dividing a memory area of the semiconductor memory device, wherein data is selectively stored in said blocks and batch-erased from said blockselectively storing data and batch-erasing data in units of a block;

storing "empty state"-indicative data indicating absence of data in at least one of the memory positions of the table memory which corresponds to at least one of the blocks which contains no data; and

detecting at least one empty block by searching the table memory for the "empty state"-indicative data in a data writing mode.

10. The method according to claim 9, which includes designating the memory positions of the table memory by means of the addresses allocated to the blocks, respectively.

11. The method according to claim 9, wherein includes searching for "empty state"-indicative data stored in the memory positions of the table memory in a predetermined sequence, stopping searching of the "empty state"-indicative data in response to a first detection of one of the memory positions corresponding to one of -the blocks which is in an empty state in the semiconductor memory device, and generating address data for designating the detected one of the block which is in an empty state.

12. The method according to claim 11, which includes updating the "empty state"-indicative data stored in the memory position of the table memory which corresponds to one of the blocks which is designated by the address data and in which new data is written, to "non-empty state"-indicative data.

13. The method according to claim 11, which includes updating the "non-empty state"-indicative data stored in one of the memory positions of the table memory which corresponds to one of the blocks of the semiconductor memory which has been subjected to a batch erasure, to "empty state"-indicative data.

14. A memory control method according to claim 9, which includes a step of converting a logical address from the host computer into a physical address for the semiconductor memory device.