Method and apparatus for asynchronous device communication

• US 5,987,586 A
• Filed: 12/23/1993
• Issued: 11/16/1999
• Est. Priority Date: 12/23/1993
• Status: Expired due to Fees

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Byers, Larry L.
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US08/173,408
• Time in Patent Office: 2,154 Days
• Field of Search: 395/800, 395/775, 395/725, 395/425, 395/275, 395/200, 395/250, 367/117, 367/135, 367/137, 370/53, 370/61, 370/91, 370/463, 370/357, 370/428, 371/11.2, 371/8.2, 371/21.1, 371/68.1, 371/68.2, 371/68.3, 714/820, 714/821, 712/11, 769/248, 769/250, 769/234, 710/129, 710/130, 710/131, 369/176
• US Class Current: 712/11
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

An apparatus for and method of providing rapid communication between separately clocked system elements. A network interface module is used as the overall system control and communication interface to each of the separate system elements. Each of these system elements is controlled by a different and dedicated programmable micro-engine. A separate register located within and addressable by each of the micro-engines provides the basic data transfer path. Access by a micro-engine to the corresponding register is easily accomplished by firmware. The bit serial scan interface between the network interface module and each of the registers is controlled by the network interface module.

Claims

1. In a digital data processing system having a system element embedded in a parallel processing architecture, an apparatus comprising:

a. a micro-engine for controlling said system element;

b. a register located within and directly addressable by said micro-engine; and

c. a network interface module, having a point-to-point interface, which is timed asynchronously with respect to said micro-engine and which is coupled to said register through said point-to-point interface whereby said network interface module writes into and reads from said register through said point-to-point interface.

2. An apparatus according to claim 1 further comprising:

a. a second micro-engine for controlling a second system element; and

b. a second register located within and directly addressable by said second micro-engine and coupled to said network interface module whereby said network interface module writes into and reads from said second register.

3. An apparatus according to claim 1 wherein said register is a dynamic register.

4. An apparatus according to claim 2 wherein said second register is a dynamic register.

5. A method of communicating between a first system element and a second micro-engine controlled system element, wherein said first system element is timed asynchronously with respect to said second micro-engine controlled system element, comprising:

a. writing data from said first system element into a register located within said second micro-engine controlled system element; and

b. reading said data from said register by said second micro-engine controlled system element.

6. A method of communicating between a first system element and a second micro-engine controlled system element, wherein said first system element is timed asynchronously of said second micro-engine controlled system element, comprising;

a. writing data into a register within said second micro-engine controlled system element by said second system element; and

b. reading said data from said register by said first system element.

7. In a digital data element and system employing a first system element and a second system element and wherein said first system element is controlled by a micro-engine and wherein said first system element is timed asynchronously with respect to said second system element, the improvement comprising:

a. a dynamic register located within said second system element; and

b. an interface between said first system element and said dynamic register whereby said first system element writes into and reads from said dynamic register.

8. The improvement of claim 7 wherein said second system element is coupled to said dynamic register whereby said second system element writes into and reads from said dynamic register.

9. The improvement of claim 8 wherein said dynamic register accommodates a plurality of bit positions in parallel.

10. The improvement of claim 9 wherein said interface accommodates said plurality of bit positions in parallel.

11. A method of communicating a micro-engine controlled system element having an addressable register, and a system element, wherein said system element operates asynchronously with respect to said micro-engine controlled system element, comprising:

a. writing data from the micro-engine controlled system element into the register; and

b. asynchronously reading said data from the register by the system element.