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Fabrication method of a vertical channel transistor

  • US 5,989,961 A
  • Filed: 07/17/1998
  • Issued: 11/23/1999
  • Est. Priority Date: 12/17/1997
  • Status: Expired due to Term
First Claim
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1. A method for manufacturing a vertical channel transistor comprising the steps of:

  • a) selectively implanting a dopant of high concentration into a semiconductor substrate to form a source region;

    b) firstly etching the semiconductor substrate using an insulator and a first photoresist pattern as a mask;

    c) secondly etching the substrate using a second photoresist pattern having a shape corresponding to said source region as a mask;

    d) implanting a dopant of low concentration into the exposed substrate using said second photoresist pattern as a mask to form a vertical channel layer;

    e) implanting a dopant of high concentration into the exposed substrate using same mask to form a drain region;

    f) activating said dopants, and forming an ohmic contact layer on said drain region;

    g) thirdly etching using a third photoresist pattern for exposing the firstly etched portion of the substrate as a mask;

    h) depositing a gate metal on the substrate exposed by the thirdly etching;

    i) forming a interlayer dielectric film, and forming an ohmic contact layers on the remained source region; and

    j) opening the source, the drain and the gate, and wiring a metal, respectively.

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