Fabrication method of a vertical channel transistor

• US 5,989,961 A
• Filed: 07/17/1998
• Issued: 11/23/1999
• Est. Priority Date: 12/17/1997
• Status: Expired due to Term

• Current Assignee: Electronics and Telecommunications Research Institute, Korea Telecom (KT Corporation)
• Original Assignee: Electronics and Telecommunications Research Institute, Korea Telecom (KT Corporation)
• Inventors: Oh, Eung Gie, Yang, Jeon Wook, Mun, Jae Kyoung, Lee, Jae Jin, Pyun, Kwang Eui
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US09/116,904
• Time in Patent Office: 494 Days
• Field of Search: 438/212, 438/268, 438/270, 438/271, 438/272
• US Class Current: 438/270
• CPC Class Codes: H01L 29/66856 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802

Abstract

Disclosed is a method for manufacturing a vertical channel transistor comprising the steps of: selectively implanting a dopant of high concentration into a semiconductor substrate to form a source region; firstly etching the semiconductor substrate using an insulator and a first photoresist pattern as a mask; secondly etching the substrate using a second photoresist pattern having a shape corresponding to said source region as a mask; implanting a dopant of low concentration into the exposed substrate using said second photoresist pattern as a mask to form a vertical channel layer; implanting a dopant of high concentration into the exposed substrate using same mask to form a drain region; activating said dopants, and forming an ohmic contact layer on said drain region; thirdly etching using a third photoresist pattern for exposing the firstly etched portion of the substrate as a mask; depositing a gate metal on the substrate exposed by the thirdly etching; and wiring a metal, respectively. This invention can be easily manufactured a vertical channel transistor having a low parasitic resistance and an extremely small gate length without sophicated complex processes.

Claims

1. A method for manufacturing a vertical channel transistor comprising the steps of:

a) selectively implanting a dopant of high concentration into a semiconductor substrate to form a source region;

b) firstly etching the semiconductor substrate using an insulator and a first photoresist pattern as a mask;

c) secondly etching the substrate using a second photoresist pattern having a shape corresponding to said source region as a mask;

d) implanting a dopant of low concentration into the exposed substrate using said second photoresist pattern as a mask to form a vertical channel layer;

e) implanting a dopant of high concentration into the exposed substrate using same mask to form a drain region;

f) activating said dopants, and forming an ohmic contact layer on said drain region;

g) thirdly etching using a third photoresist pattern for exposing the firstly etched portion of the substrate as a mask;

h) depositing a gate metal on the substrate exposed by the thirdly etching;

i) forming a interlayer dielectric film, and forming an ohmic contact layers on the remained source region; and

j) opening the source, the drain and the gate, and wiring a metal, respectively.

2. The method as claimed in claim 1, wherein said semiconductor substrate is made of a gallium arsenide substrate.

3. The method as claimed in claim 1, wherein said firstly etching uses an anisotropic etching so as to etch vertically toward the substrate.

4. The method as claimed in claim 1, wherein the etched depth of firstly etching is more deep than that of the source region.

5. The method as claimed in claim 1, wherein said implanting step of (d) is inclined doped by tilting the substrate so as to form the vertical channel layer with uniform doping level.

6. The method as claimed in claim 1, wherein said thirdly etching step uses an isotropic etching so as to control the thickness of the vertical channel layer and the size of the source.