Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture

• US 5,990,021 A
• Filed: 12/19/1997
• Issued: 11/23/1999
• Est. Priority Date: 12/19/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E., Prall, Kirk, Ireland, Philip J., Sharan, Sujit, Sandhu, Gurtel
• Primary Examiner(s): Utech, Benjamin
• Assistant Examiner(s): Vinh, Lan
• Application Number:
  US08/994,950
• Time in Patent Office: 704 Days
• Field of Search: 438/745, 438/754, 438/755, 438/756, 438/757, 438/753
• US Class Current: 438/745
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

This invention is a process for manufacturing a random access memory array. Each memory cell within the array which results from the process incorporates a stacked capacitor, a silicon nitride coated access transistor gate electrode, and a self-aligned high-aspect-ratio digit line contact having a tungsten plug which extends from the substrate to a metal interconnect structure located at a level above the stacked capacitor. The contact opening is lined with titanium metal which is in contact with the substrate, and with titanium nitride that is in contact with the plug. Both the titanium metal and the titanium nitride are deposited via chemical vapor deposition reactions.

Claims

1. A process for forming a digit line contact in an array of dynamic random access memory cells, said array being constructed on a silicon substrate and having a capacitor for each cell, said array having an interlevel dielectric layer which blankets the entire array and which covers each capacitor, each cell within said array having a field-effect access transistor with a gate electrode which, on its top and sides, is completely encased by a dielectric material, said interlevel dielectric layer being anisotropically and selectively etchable with respect to the dielectric material, each of said transistors having a storage-node junction coupled to one of the capacitors and an access-node junction to which digit line contact must be made, said process comprising the steps of:

anisotropically etching digit line contact openings through the interlevel dielectric layer so as to expose an underlying access-node junction, each digit line contact opening being self-aligned to the dielectric material on a side of at least one transistor gate electrode, each digit line contact opening having a bottom opening exposing the underlying access-node junction and having a sidewall;

depositing a titanium metal layer via chemical vapor deposition, said titanium metal layer lining covering the bottom opening exposing the underlying access-node junction and the sidewall of each contact opening;

depositing a titanium nitride layer via chemical vapor deposition, said titanium nitride layer covering the titanium metal layer covering the bottom opening exposing the underlying access-node junction and on the sidewall of each contact opening;

forming tungsten plugs within the contact openings lined with titanium metal and titanium nitride, the tungsten plugs in contact with the titanium nitride layer covering the bottom opening exposing the underlying access-node junction and on the sidewall of each contact opening; and

forming metal interconnect lines on an upper surface of the interlevel dielectric layer, each line of the metal interconnect lines contacting a plurality of tungsten plugs.

2. The process of claim 1, which further comprises the step of planarizing the interlevel dielectric layer prior to etching the digit line contact openings.

3. The process of claim 1, wherein the titanium metal layer is subjected to an elevated temperature anneal step in order to convert at least a portion of the titanium metal layer which overlies and covers the bottom opening of each contact opening exposing the underlying access-node junction of each transistor on the silicon substrate to titanium silicide.

4. A process for fabricating an integrated circuit, said process comprising the steps of:

forming field-effect transistor gates and gate interconnects on a horizontally-oriented substrate, said word lines having a lower surface which is dielectrically insulated from the substrate by a gate dielectric layer, said word lines also having an upper surface and sidewalls which are covered by a word line isolation layer comprising a first dielectric material;

depositing an interlevel dielectric layer, said interlevel dielectric layer comprising a second dielectric material, said second dielectric material being selectively etchable with respect to said first dielectric material;

etching a plurality of vertically-oriented contact openings through said interlevel dielectric layer, each of said contact openings having a bottom opening exposing a junction in the substrate which is adjacent at least one word line and a sidewall, each of said contact openings at least partially overlapping the word line isolation layer on the sidewall of said at least one adjacent word line;

lining the bottom opening and the sidewall of each contact opening with a titanium metal layer to provide a titanium metal lined contact opening;

lining each titanium metal lined contact opening with a titanium nitride layer to provide a double lined contact opening while maintaining a portion of each contact opening free of titanium metal and titanium nitride;

forming a tungsten metal plug within each double lined contact opening in contact with the titanium nitride layer; and

forming a plurality of metal digit lines, each digit line being in physical and electrical contact with multiple metal plugs.

5. The process of claim 4, wherein said integrated circuit is a dynamic random access memory array and the process further comprises the step of fabricating a stacked capacitor for each memory cell within the memory array.

6. The process of claim 5, wherein the interlevel dielectric layer is deposited to a depth to completely cover the stacked capacitors.

7. The process of claim 4, wherein the interlevel dielectric layer is planarized prior to etching the contact openings.

8. The process of claim 4, wherein the titanium metal layer is subjected to an elevated temperature anneal step in order to convert at least a portion of the titanium metal layer which overlies a bottom opening of a contact opening exposing a junction in the substrate to titanium silicide.

9. A process for manufacturing an array of dynamic random access memory cells on a silicon substrate, said process comprising the steps of:

forming a field oxide pattern on particular regions of the substrate which will function as isolation areas;

forming a gate dielectric layer on other regions of the substrate which will function as active areas;

forming a triple-layer sandwich having a polycrystalline silicon layer in contact both with an upper surface of the gate dielectric layer and an upper surface of the field oxide pattern, a refractory metal silicide layer on top of the polycrystalline silicon layer, and a silicon nitride layer on top of the silicide layer;

forming word lines from the triple-layer sandwich by forming a mask pattern on the sandwich and etching the sandwich with an anisotropic plasma etch, each of said word lines having vertical sidewalls, each of said word lines forming an access transistor gate where it overlies the gate dielectric layer, and forming an access transistor gate interconnect where it overlies field oxide;

forming access transistor source/drain regions on opposite sides of the word lines within the active areas;

forming silicon nitride spacers on the word line sidewalls;

forming a stacked capacitor for each memory cell, each capacitor being electrically coupled to a source/drain region which is to function as a storage-node junction;

depositing an interlevel dielectric layer which covers the stacked capacitors;

anisotropically etching digit line contact openings through the interlevel dielectric layer to the underlying source/drain regions which will function as access-node junctions, each contact opening having a bottom opening and a sidewall, each of said access-node junctions being shared by a pair of adjacent access transistors, said digit line contact openings being self-aligned to a gate sidewall spacer of each transistor of each adjacent access transistor pair, none of said contact openings exposing either the polycrystalline silicon layer or the silicide layer which comprise a gate of either adjacent transistor;

depositing a titanium metal layer via chemical vapor deposition, said titanium metal layer lining the sidewall of each contact opening and covering the exposed source/drain region at the bottom opening of each contact opening;

depositing a titanium nitride layer via chemical vapor deposition, said titanium nitride layer covering the titanium metal layer on the sidewall of each contact opening and covering the titanium metal layer covering the exposed source/drain region at the bottom opening of each contact opening;

depositing a tungsten layer via chemical vapor deposition which fills the contact openings in contact with the titanium nitride layer;

removing the titanium metal layer, the titanium nitride layer and the tungsten layer from an upper surface of the interlevel dielectric layer to leave a tungsten plug within each contact opening; and

forming metal interconnect lines on the upper surface of the interlevel dielectric layer, each of which makes contact to a plurality of tungsten plugs.

10. The process of claim 9, wherein the interlevel dielectric layer is planarized prior to etching the digit line contact openings.

11. The process of claim 9, wherein the titanium metal layer is subjected to an elevated temperature anneal step in order to convert at least a portion of the titanium metal layer which overlies the exposed source/drain region at the bottom opening of each contact opening on the silicon substrate to titanium silicide.