Circuit structure which avoids latchup effect

• US 5,990,523 A
• Filed: 05/06/1999
• Issued: 11/23/1999
• Est. Priority Date: 05/06/1999
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Integrated Circuits Corp. (United Microelectronics Corporation)
• Inventors: Hsia, Liang-Choo
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Hu, Shouxiang
• Application Number:
  US09/306,114
• Time in Patent Office: 201 Days
• Field of Search: 257/372, 257/373, 257/369, 257/394, 257/547, 326/15, 326/33, 326/34, 326/83, 326/121, 326/110, 326/81, 326/108, 326/112, 326/119, 327/210, 327/310, 327/312, 327/313, 327/389, 327/390, 327/433, 327/437, 327/576, 327/538
• US Class Current: 257/372
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Abstract

A circuit structure which avoids a latchup effect. An N-well is formed in a P-type substrate. An N-type contact is formed in the N-well. A PMOS is located on the N-well. A gate of the PMOS connects to an input terminal and a source region of the PMOS connects to a voltage source. A first NMOS and a second NMOS are located on the P-type substrate. A gate of the first NMOS connects to the input terminal, a source region of the first NMOS connects to a ground terminal, and a drain region of the first NMOS connects to an output terminal and a drain region of the PMOS. A gate of the second NMOS connects to the output terminal, a source region of the second NMOS connects to a voltage source, and a drain region of the second NMOS connects to the N-type contact.

Claims

1. A circuit structure which avoids a latchup effect, the circuit structure comprising:

a substrate;

an N-type doped region in the substrate;

an N-type contact in the N-type doped region;

a P-type metal oxide semiconductor on the N-type doped region, wherein a gate of the P-type metal oxide semiconductor connects to an input terminal, and a source region of the P-type metal oxide semiconductor connects to a voltage source;

a first N-type metal oxide semiconductor on the substrate, wherein a gate of the first N-type metal oxide semiconductor connects to the input terminal, a source region of the first N-type metal oxide semiconductor connects to a ground terminal, and a drain region of the first N-type metal oxide semiconductor connects to a drain region of the P-type metal oxide semiconductor and an output terminal; and

a second N-type metal oxide semiconductor on the substrate, wherein a gate of the second N-type metal oxide semiconductor connects to the output terminal, a drain region of the second N-type metal oxide semiconductor connects to the voltage source, and a source region of the second N-type metal oxide semiconductor connects to the N-type contact.

2. A circuit structure which avoids a latchup effect, the circuit structure comprising:

a semiconductor substrate;

a doped region in the semiconductor substrate;

a contact whose type is the same as the doped region in the doped region;

a first MOS whose type is different from the doped region, wherein a gate of the first MOS connects to an input terminal, and a source region of the first MOS connects to a voltage source;

a second MOS whose type is the same as the doped region on the semiconductor substrate, wherein a gate of the second MOS connects to the input terminal, a source region of the second MOS connects to a ground terminal, and a drain region of the second MOS connects to a drain region of the first MOS and an output terminal; and

a third MOS whose type is the same as the doped region on the semiconductor substrate, wherein a gate of the third MOS connects to the output terminal, a drain region of the third MOS connects to the voltage source, and a source region of the third MOS connects to the contact.

3. The circuit structure of claim 2, wherein impurities doped in the doped region are N-type.

4. A circuit structure which avoids a latchup effect, the circuit structure comprising:

a substrate;

an N-type doped region in the substrate;

an N-type contact in the N-type doped region;

a P-type metal oxide semiconductor on the N-type doped region, wherein a source region of the P-type metal oxide semiconductor connects to a voltage source;

a first N-type metal oxide semiconductor on the substrate, wherein a source region of the first N-type metal oxide semiconductor connects to a ground terminal, and a drain region of the first N-type metal oxide semiconductor connects to a drain region of the P-type metal oxide semiconductor; and

second N-type metal oxide semiconductor on the substrate, wherein a gate of the second N-type metal oxide semiconductor connects to a drain region of the P-type metal oxide semiconductor, a drain region of the second N-type metal oxide semiconductor connects to the voltage source, and a source region of the second N-type metal oxide semiconductor connects to the N-type contact.

5. A circuit which avoids a latchup effect, the circuit comprising:

a P-type metal oxide semiconductor, wherein a source region of the P-type metal oxide semiconductor connects to a voltage source;

a first N-type metal oxide semiconductor, wherein a source of the first N-type metal oxide semiconductor connects to a ground terminal and a drain region of the first N-type metal oxide semiconductor connects to a drain region of the P-type metal oxide semiconductor; and

a second N-type metal oxide semiconductor, wherein a gate of the second N-type metal oxide semiconductor connects to the drain region of the P-type metal oxide semiconductor, a drain region of the second N-type metal oxide semiconductor connects to the voltage source, and a source region of the second N-type metal oxide semiconductor connects to a doped well region in a semiconductor substrate of the P-type metal oxide semiconductor.

6. The circuit of claim 5, wherein a gate of the P-type metal oxide semiconductor connects to a gate of the first N-type metal oxide semiconductor.

7. The circuit of claim 5, further comprising:

a NAND gate having a first input terminal, a second input terminal and a first output terminal, wherein the first output terminal connects to the gate of the P-type metal oxide semiconductor;

a NOR gate having a third input terminal, a fourth input terminal and a second output terminal, wherein the second output terminal connects to the gate of the N-type metal oxide semiconductor and the fourth input terminal connects to the second input terminal;

a converter having a fifth input terminal and a third output terminal, wherein the fifth input terminal connects to the first input terminal and the third output terminal connects to the third input terminal.

8. The circuit of claim 5, further comprising:

a NAND gate having two input terminals and an output terminal, wherein the output terminal of the NAND gate connects to an input terminal of the P-type metal oxide semiconductor;

a NOR gate having two input terminals and an output terminal, wherein the output terminal of the NOR gate connects to an input terminal of the N-type metal oxide semiconductor and one input terminal of the NOR gate connects to one input terminal of the NAND gate; and

a converter having an input terminal and an output terminal, wherein the input terminal of the converter connects to the other input terminal of the NAND gate and the output terminal of the converter connects to the other input terminal of the NOR gate.