Raised semiconductor MOS transistor with improved transistor characteristics

• US 5,990,530 A
• Filed: 07/14/1997
• Issued: 11/23/1999
• Est. Priority Date: 07/15/1996
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation), Sony Corporation (Sony Group Corp.)
• Original Assignee: NEC Corporation
• Inventors: Suzuki, Hisamitsu
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US08/892,028
• Time in Patent Office: 862 Days
• Field of Search: 257/335, 257/336, 257/344, 257/342, 257/374, 257/377, 257/382-385, 257/408, 257/355
• US Class Current: 257/408
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation

Abstract

A semiconductor device including a semiconductor substrate having thereon an element region having a surface, an element separating insulating film having an upper surface adjacent to opposing lateral sides of the element region, a silicon epitaxial layer having an upper surface formed on the surface of the element region, a polysilicon layer having an upper surface formed on the element separating film and connected to the silicon epitaxial layer, a gate insulating film and a gate electrode formed on the silicon epitaxial layer, and impurity doped source and drain regions formed in the silicon epitaxial layer. Furthermore, the upper surface of the silicon epitaxial layer is higher than or at the same level as the upper surface of the polysilicon layer. This is done by forming the polysilicon layer on a recessed portion of the element separating insulating film adjacent to the element region. The above prevents the occurrence of overhanging structures which would otherwise partially block the source and drain implant and result in a high resistance region.

Claims

1. A semiconductor device comprising a semiconductor substrate having thereon

an element region having a surface,

an element separating insulating film having an upper surface, adjacent to opposing lateral sides of said element region,

a silicon epitaxial layer having an upper surface, formed on the surface of said element region,

a polysilicon layer having an upper surface formed on said element separating film and connected to said silicon epitaxial layer,

a gate insulating film and a sate electrode formed on said silicon epitaxial layer, and

impurity doped source and drain regions formed in said silicon epitaxial layer to the sides of the gate electrode and adjacent said element separating film,

wherein the upper surface of said silicon epitaxial layer is higher than or at the same level as the upper surface of said polysilicon layer and

wherein the upper surface of said element separating film is lower than the surface of said element region.

2. The semiconductor device as claimed in claim 1, further comprising a side wall oxide film formed on a side surface of said gate electrode, and said silicon epitaxial layer including a channel doped region below the gate electrode, a LDD region formed below the side wall oxide film of the gate electrode, and source and drain regions formed between an outside edge of the side wall oxide film and the element separating film on opposing lateral sides of said element region.

3. The semiconductor device as claimed in claim 1, wherein a channel doped layer having an impurity concentration high enough to prevent punch-through between the source and drain is provided in the silicon epitaxial layer below said gate electrode.

5. The semiconductor device as claimed in claim 3, wherein said second polysilicon layer is a selective polysilicon layer and said silicon epitaxial layer is a selective silicon epitaxial layer.

4. A semiconductor device comprising a semiconductor substrate having thereon

an element region having a surface,

an element separating insulating film having an upper surface, adjacent to opposing lateral sides of said element region,

a silicon enitaxial layer having an upper surface, formed on the surface of said element region,

a polysilicon layer having an upper surface formed on said element separating film and connected to said silicon epitaxial layer,

a gate insulating film and a gate electrode formed on said silicon epitaxial layer, and

impurity doped source and drain regions formed in said silicon epitaxial layer to the sides of the gate electrode and adjacent said element separating film,

wherein the upper surface of said silicon epitaxial layer is higher than or at the same level as the upper surface of said polysilicon layer and

wherein said polysilicon layer comprises a first polysilicon layer formed on the element separating film and a second polysilicon layer formed on said first polysilicon layer.

6. A semiconductor device comprising a semiconductor substrate having thereon

an element region having a surface,

an element separating insulating film having an upper surface, adjacent to opposing lateral sides of said element region,

a silicon epitaxial layer having an upper surface, formed on the surface of said element region,

a polysilicon layer having an upper surface formed on said element separating film and connected to said silicon epitaxial layer,

a gate insulating film and a gate electrode formed on said silicon epitaxial layer,

impurity doped source and drain regions formed in said silicon epitaxial layer to the sides of the gate electrode and adjacent said element separating film, and

silicide layers formed on an upper surface of said gate electrode, on said polysilicon layer and on said silicon epitaxial layer, and source and drain electrodes each connected to said silicide layer formed on said polysilicon layer at opposing lateral sides of said element region,

wherein the upper surface of said silicon epitaxial layer is higher than or at the same level as the upper surface of said polysilicon layer.

7. A semiconductor device comprising a semiconductor substrate having thereon an element region, an element separating insulating film adjacent to opposing lateral sides of said element region, a first silicon epitaxial layer formed on said element region, a second silicon epitaxial layer having an upper surface, formed on said first silicon epitaxial layer, a polysilicon layer including an upper surface formed on said element separating film and connected to said second silicon cpitaxial layer, a gate insulating film and a gate electrode formed on said second silicon epitaxial layer, and impurity doped source and drain regions formed in said second silicon epitaxial layer to the sides of the gate electrode and adjacent said element separating film,

wherein the upper surface of said second silicon epitaxial layer is higher than or at the same level as the upper surface of said polysilicon layer.

8. The semiconductor device as claimed in claim 7, wherein said polysilicon layer comprises a first polysilicon layer formed on the element separating film and a second polysilicon layer formed on said first polysilicon layer.

9. The semiconductor device as claimed in claim 8, wherein said second polysilicon layer is a selective polysilicon layer and said first and second silicon epitaxial layers are selective silicon epitaxial layers.

10. The semiconductor device as claimed in claim 7, further comprising silicide layers formed on an upper surface of said gate electrode, on said polysilicon layer and on said second silicon epitaxial layer, and source and drain electrodes each connected to said silicide layer formed on said polysilicon layer at opposing lateral sides of said element region.

11. The semiconductor device as claimed in claim 7, further comprising a side wall oxide film formed on a side surface of said gate electrode, and said second silicon epitaxial layer including a channel doped region below the gate electrode, a LDD region formed below the side wall oxide film of the gate electrode, and source and drain regions formed between an outside edge of the side wall oxide film and the element separating film on opposing lateral sides of said element region.

12. The semiconductor device as claimed in claim 7, wherein a channel doped layer having an impurity concentration high enough to prevent punch-through between the source and drain is provided in a silicon epitaxial layer below said gate electrode.

13. A semiconductor device comprising a semiconductor substrate having thereon an element region, an element separating insulating film adjacent to opposing lateral sides of said element region, a silicon epitaxial layer having an upper surface formed on said element region, a first polysilicon layer formed on said element separating film, a second polysilicon layer having an upper surface formed on said first polysilicon layer and connected to said silicon epitaxial layer, a gate insulating film and a gate electrode formed on said silicon epitaxial layer, and impurity doped source and drain regions formed in said silicon epitaxial layer,

wherein the upper surface of said silicon epitaxial layer is lower than the upper surface of said second polysilicon layer, the first polysilicon layer has a tapered edge adjacent the element region, and the bottom of the first polysilicon layer is closer to the element region than the top of the first polysilicon layer.

14. The semiconductor device as claimed in claim 13, further comprising silicide layers formed on an upper surface of said gate electrode, on said second polysilicon layer and on said silicon epitaxial layer, and source and drain electrodes each connected to said silicide layer formed on said second polysilicon layer at opposing lateral sides of said element region.