Differential amplifier circuit
First Claim
1. A differential amplifier comprising:
- a differential input circuit having first and second input terminals for receiving first and second input signals, and amplifying a potential difference between the two input signals, and having first and second output terminals for outputting first and second voltage signals, respectively, the first and second voltage signals representing the amplified potential difference between the two input signals;
a third output terminal for outputting a third output signal of the differential amplifier;
a first output transistor connected between a high potential power supply and the third output terminal for pulling-up a potential at the third output terminal wherein the first output transistor includes a P-channel MOS transistor;
a second output transistor connected between the third output terminal and a low potential power supply for pulling-down the potential at the third output terminal wherein the second output transistor includes an N-channel MOS transistor; and
a gate voltage controller connected to the first and second output terminals for receiving the first and second voltage signals, respectively, and for controlling voltages applied to each of the gate terminals of the first and second output transistors based on the first and second voltage signals to control the currents flowing to the first and second output transistors;
wherein the gate voltage controller applies a voltage level substantially equal to the low potential power supply to the gate terminal of the first output transistor when turning on the first output transistor for pull-up operation, and wherein applies a voltage level substantially equal to the high potential power supply to the gate terminal of the second output transistor when turning on the second output transistor for pull-down operation;
wherein the gate voltage controller applies a voltage that is higher than that of the low potential power supply by a predetermined voltage to the gate terminal of the first output transistor for pull-up operation, and applies a voltage that is lower than that of the high potential power supply by the predetermined voltage to the gate terminal of the second output transistor for pull-down operation;
wherein the predetermined voltage is a source-drain voltage of a MOS transistor at an on-state.
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Accused Products
Abstract
A differential amplifier circuit includes a differential input circuit which receives first and second input signals. The differential input circuit amplifies a potential difference between the input signals and outputs first and second voltage signals at first and second output terminals representing the amplified potential difference. A first output transistor is connected between a high potential power supply and a third output terminal of the differential input circuit. The first output transistor pulls up the potential at the third output terminal. A second output transistor is connected between the third output terminal and a low potential power supply for pulling down the potential at the third output terminal. A gate voltage controller is connected to the first and second output terminals and receives the first and second voltage signals and controls voltages applied to each of the gate terminals of the first and second output transistors to control the currents flowing to them.
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Citations
22 Claims
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1. A differential amplifier comprising:
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a differential input circuit having first and second input terminals for receiving first and second input signals, and amplifying a potential difference between the two input signals, and having first and second output terminals for outputting first and second voltage signals, respectively, the first and second voltage signals representing the amplified potential difference between the two input signals; a third output terminal for outputting a third output signal of the differential amplifier; a first output transistor connected between a high potential power supply and the third output terminal for pulling-up a potential at the third output terminal wherein the first output transistor includes a P-channel MOS transistor; a second output transistor connected between the third output terminal and a low potential power supply for pulling-down the potential at the third output terminal wherein the second output transistor includes an N-channel MOS transistor; and a gate voltage controller connected to the first and second output terminals for receiving the first and second voltage signals, respectively, and for controlling voltages applied to each of the gate terminals of the first and second output transistors based on the first and second voltage signals to control the currents flowing to the first and second output transistors; wherein the gate voltage controller applies a voltage level substantially equal to the low potential power supply to the gate terminal of the first output transistor when turning on the first output transistor for pull-up operation, and wherein applies a voltage level substantially equal to the high potential power supply to the gate terminal of the second output transistor when turning on the second output transistor for pull-down operation; wherein the gate voltage controller applies a voltage that is higher than that of the low potential power supply by a predetermined voltage to the gate terminal of the first output transistor for pull-up operation, and applies a voltage that is lower than that of the high potential power supply by the predetermined voltage to the gate terminal of the second output transistor for pull-down operation; wherein the predetermined voltage is a source-drain voltage of a MOS transistor at an on-state. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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2. A differential amplifier comprising:
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a differential input circuit having first and second input terminals for receiving first and second input signals, and amplifying a potential difference between the two input signals, and having first and second output terminals for outputting first and second voltage signals, respectively, the first and second voltage signals representing the amplified potential difference between the two input signals; a third output terminal for outputting a third output signal of the differential amplifier; a first output transistor connected between a high potential power supply and the third output terminal for pulling-up a potential at the third output terminal wherein the first output transistor includes a P-channel MOS transistor; a second output transistor connected between the third output terminal and a low potential power supply for pulling-down the potential at the third output terminal wherein the second output transistor includes an N-channel MOS transistor; and a gate voltage controller connected to the first and second output terminals for receiving the first and second voltage signals, respectively, and for controlling voltages applied to each of the gate terminals of the first and second output transistors based on the first and second voltage signals to control the currents flowing to the first and second output transistors; wherein the gate voltage controller applies a voltage level substantially equal to the low potential power supply to the gate terminal of the first output transistor when turning on the first output transistor for pull-up operation, and wherein applies a voltage level substantially equal to the high potential power supply to the gate terminal of the second output transistor when turning on the second output transistor for pull-down operation, wherein the gate voltage controller applies a voltage that is higher than that of the low potential power supply by a predetermined voltage to the gate terminal of the second output transistor for pull-up operation, and applies a voltage that is lower than that of the high potential power supply by the predetermined voltage to the gate terminal of the first output transistor for pull-down operation; wherein the predetermined voltage is a source-drain voltage of a MOS transistor at an on-state.
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13. A differential amplifier circuit having first and second input terminals for receiving first and second input signals and an output terminal, comprising:
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a current mirror circuit including a first current mirror transistor and a second current mirror transistor, wherein a source of the first and second current mirror transistors is connected to a high potential power supply, a gate of the first current mirror transistor is connected to its drain and to a gate of the second current mirror transistor, and a drain of the first current mirror transistor is connected to a low potential power supply by way of a current source; a differential input circuit connected to the first and second input terminals for receiving the first and second input signals and amplifying a potential difference between the first and second input signals, and generating first and second voltage signals representing the potential difference, and the differential input circuit connected to the current mirror circuit; a first output transistor connected between the high potential power supply and the output terminal; a second output transistor connected between the output terminal and the low potential power supply; and a gate control voltage controller, connected to the differential input circuit and receiving the first and second voltage signals, for controlling voltages applied to the gates of the first and second output transistors based on the first and second voltage signals to control the currents flowing through the first and second output transistors, wherein the gate voltage controller applies a voltage level substantially equal to the low potential power supply to the gate terminal of the first output transistor when turning on the first output transistor and applies a voltage level substantially equal to the high potential power supply to the gate terminal of the second output transistor when turning on the second output transistor. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification