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Differential amplifier circuit

  • US 5,990,742 A
  • Filed: 05/13/1998
  • Issued: 11/23/1999
  • Est. Priority Date: 11/26/1997
  • Status: Expired due to Term
First Claim
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1. A differential amplifier comprising:

  • a differential input circuit having first and second input terminals for receiving first and second input signals, and amplifying a potential difference between the two input signals, and having first and second output terminals for outputting first and second voltage signals, respectively, the first and second voltage signals representing the amplified potential difference between the two input signals;

    a third output terminal for outputting a third output signal of the differential amplifier;

    a first output transistor connected between a high potential power supply and the third output terminal for pulling-up a potential at the third output terminal wherein the first output transistor includes a P-channel MOS transistor;

    a second output transistor connected between the third output terminal and a low potential power supply for pulling-down the potential at the third output terminal wherein the second output transistor includes an N-channel MOS transistor; and

    a gate voltage controller connected to the first and second output terminals for receiving the first and second voltage signals, respectively, and for controlling voltages applied to each of the gate terminals of the first and second output transistors based on the first and second voltage signals to control the currents flowing to the first and second output transistors;

    wherein the gate voltage controller applies a voltage level substantially equal to the low potential power supply to the gate terminal of the first output transistor when turning on the first output transistor for pull-up operation, and wherein applies a voltage level substantially equal to the high potential power supply to the gate terminal of the second output transistor when turning on the second output transistor for pull-down operation;

    wherein the gate voltage controller applies a voltage that is higher than that of the low potential power supply by a predetermined voltage to the gate terminal of the first output transistor for pull-up operation, and applies a voltage that is lower than that of the high potential power supply by the predetermined voltage to the gate terminal of the second output transistor for pull-down operation;

    wherein the predetermined voltage is a source-drain voltage of a MOS transistor at an on-state.

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