Method for implementing the power function DP and computer graphics system employing the same

• US 5,990,894 A
• Filed: 06/16/1997
• Issued: 11/23/1999
• Est. Priority Date: 06/16/1997
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Hu, Vernon J. H., Peterson, Donald A.
• Primary Examiner(s): Nguyen, Phu K.
• Assistant Examiner(s): Vo, Cliff N.
• Application Number:
  US08/876,928
• Time in Patent Office: 890 Days
• Field of Search: 345/418, 345/419, 345/420, 345/423, 345/424, 345/425
• US Class Current: 345/418
• CPC Class Codes: G06F 1/0307 Logarithmic or exponential functions G06F1/0314, G06F1/035 take precedence

Abstract

A graphics accelerator using an improved method for evaluating a power function. As part of determining realistic shading for objects in a three-dimensional scene, the Phong technique requires repeated evaluation of the power function D^P, where D is a base value and P is a power value with a fractional component. In one embodiment, a hardware implementation of this function determines the logarithm log₂ (D^P) using a table lookup and a multiplication. An anti-logarithm function is then performed as follows. The logarithm log₂ (D^P) is split into three parts: an integer portion I, a five bit fractional portion F, and a remainder fractional portion R. The desired value D^P is then expressible as 2^I 2^F 2^R. The factor 2^F In2 is found using a 32-entry lookup table. The factor 2^R /In2 is closely approximated by adding 1/In2 to R. Multiplying these two factors and shifting by I bits advantageously produces the desired value D^P.

Claims

1. A power function device for computing a value D^P, wherein a logarithm base two of the value, log₂ (D^P), is expressible as the combination of an integer portion I, a fixed precision fractional portion F, and a remainder portion R, and wherein the power function device comprises:

an adder coupled to receive the remainder portion R, wherein the adder is configured to add a predetermined constant to the remainder portion R to produce a first factor;

a lookup table coupled to receive the fixed-precision fractional portion F and configured to responsively provide a second factor;

a multiplier coupled to receive the first factor, wherein the multiplier is further coupled to receive the second factor, and wherein the multiplier is configured to produce a product of the first and second factors; and

a shift unit coupled to receive the product, wherein the shift unit is further coupled to receive the integer portion I, and wherein the shift unit is configured to shift the product according to the integer portion I to produce the value D^P.

2. The power function device of claim 1, wherein the predetermined constant is substantially equal to 1/ln2.

3. The power function device of claim 1, wherein the lookup table is a ROM for determining a function 2^F·

ln 2 of the fixed-precision fractional portion F.

4. The power function device of claim 1, wherein the fixed precision fractional portion F has a precision of five bits.

5. The power function device of claim 1, further comprising:

a logarithm module configured to receive a value D and to responsively produce a logarithm log₂ D; and

a multiplier unit coupled to receive the logarithm log₂ D from the logarithm module, wherein the multiplier unit is configured to receive a value P, and wherein the multiplier unit is configured to responsively produce the logarithm log₂ (D^P).

6. The power function device of claim 5, wherein the logarithm module comprises:

a leading-zeros encoder configured to receive the value D and to responsively produce a number of leading zeros in the value D;

a second shift unit configured to receive the value D, wherein the second shift unit is coupled to receive the number of leading zeros from the leading-zeros encoder, and wherein the second shift unit is configured to responsively shift the value D, thereby removing leading zeros and producing a normalized value;

a second lookup table coupled to receive the normalized value from the second shift unit and configured to responsively provide an addend; and

an adder coupled to receive the addend from the second lookup table, coupled to receive the number of leading zeros from the leading zeros encoder, and configured to provide the logarithm log₂ D by adding the addend to the number of leading zeros.

7. The power function device of claim 5, wherein the multiplier unit comprises:

a second multiplier configured to multiply a fractional portion of the value P by the logarithm log₂ D to produce an intermediate product; and

a third shift unit coupled to receive the intermediate product from the second multiplier, wherein the third shift unit is configured to shift the intermediate product by an exponent portion of the value P to produce the logarithm log₂ (D^P).

8. A computer graphics generation system comprising:

an interface module coupled to a bus for receiving image information;

a computation module coupled to receive said image information from the interface module, wherein the computation module is configured to determine realistic lighting effects based on said image information, wherein said realistic lighting effects are produced with a power function D^P, wherein D is a base value and P is a power value, wherein a logarithm log₂ (D^P) is expressible as the combination of an integer portion I, a fixed precision fractional portion F, and a remainder portion R, and wherein the computation module comprises;

an adder coupled to receive the remainder portion R, wherein the adder is configured to add a predetermined constant to the remainder portion R to produce a first factor;

a lookup table coupled to receive the fixed-precision fractional portion F and configured to responsively provide a second factor;

a multiplier coupled to receive the first factor, wherein the multiplier is further coupled to receive the second factor, and wherein the multiplier is configured to produce a product of the first and second factors; and

a shift unit coupled to receive the product, wherein the shift unit is further coupled to receive the integer portion I, and wherein the shift unit is configured to shift the product according to the integer portion I to produce a result of the power function D^P ;

a draw module coupled to receive the image information with the realistic lighting effects from the computation module, wherein the draw module is configured to responsively produce pixel data; and

an analog-to-digital converter coupled to receive the pixel data and configured to convert the pixel data into an analog video signal.

9. The computer graphics generation system of claim 8, wherein the predetermined constant is substantially equal to 1/ln2.

10. The computer graphics generation system of claim 8, wherein the lookup table is a ROM for determining a function 2^F ·

ln2 of the fixed-precision fractional portion F.

11. The computer graphics generation system claim 8, further comprising:

a logarithm module configured to receive a value D and to responsively produce a logarithm log₂ D; and

a multiplier unit coupled to receive the logarithm log₂ D from the logarithm module, wherein the multiplier unit is configured to receive a value P, and wherein the multiplier unit is configured to responsively produce the logarithm log₂ (D^P).

12. The computer graphics generation system of claim 11, wherein the logarithm module comprises:

a leading-zeros encoder configured to receive the value D and to responsively produce a number of leading zeros in the value D;

a second shift unit configured to receive the value D, wherein the second shift unit is coupled to receive the number of leading zeros from the leading-zeros encoder, and wherein the second shift unit is configured to responsively shift the value D, thereby removing leading zeros and producing a normalized value;

a second lookup table coupled to receive the normalized value from the second shift unit and configured to responsively provide an addend; and

an adder coupled to receive the addend from the second lookup table, coupled to receive the number of leading zeros from the leading zeros encoder, and configured to provide the logarithm log₂ D by adding the addend to the number of leading zeros.

13. A method for determining a power function value D^P from a base value D and a power value P, wherein the method comprises:

receiving the base value D;

determining a logarithm log₂ D using a logarithm lookup table;

receiving the power value P;

multiplying the logarithm log₂ D determined from the logarithm lookup table with the power value P to produce a logarithm log₂ (D^P) having an integer value I, a fixed-precision fractional value F, and a remainder value R;

adding 1/ln2 to the remainder value R to produce a first factor substantially equal to 2^R /ln2;

applying the fixed-precision fractional value F to an anti-log lookup table to produce a second factor substantially equal to 2^F ln2;

multiplying the first factor with the second factor to produce a product substantially equal to 2^F+R ; and

shifting the product by a number of positions indicated by the integer value I to produce the power function value D^P.

14. The method of claim 13, wherein the fixed-precision fractional value F has a precision of 5 bits.

15. The method of claim 13, wherein the determining the logarithm log₂ D comprises:

converting the base value D into a number of leading zeros;

shifting the base value D by the number of leading zeros to produce a normalized base value;

applying the normalized base value to a lookup table to produce a logarithm of the normalized base value; and

adding the number of leading zeros to the logarithm of the normalized base value to produce the logarithm log₂ D.