Method and apparatus for implementing a flush command for an accelerated graphics port device
First Claim
Patent Images
1. A method comprising:
- queuing a flush command in a first queue;
queuing a synchronization value in a second queue; and
delaying the flush command from being dequeued from the first queue until both the flush command is advanced to a head of the first queue and the synchronization value is advanced to a head of the second queue.
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Abstract
A system and method for ensuring the execution of commands is visible throughout that system. A flush command is received and enqueued in a first queue together with a synchronization value enqueued in a second queue. The flush command is delayed from being dequeued from the first queue until both the flush command and the synchronization value are advanced to the head of their respective queues. Thereafter, the flush command is dequeued subsequently causing the return of a quad-word of random data as an acknowledge signal.
35 Citations
22 Claims
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1. A method comprising:
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queuing a flush command in a first queue; queuing a synchronization value in a second queue; and delaying the flush command from being dequeued from the first queue until both the flush command is advanced to a head of the first queue and the synchronization value is advanced to a head of the second queue. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system comprising:
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a memory; a graphics controller; and a chipset coupled to both the memory and the graphics controller, the chipset including a memory controller that comprises; a command interface including a plurality of queues including a first queue adapted to enqueue the flush command and a second queue adapted to enqueue a synchronization value that includes a no-operation command processed in coordination with the flush command, and a queue advance circuit adapted to delay the flush command from being dequeued from the first queue until the synchronization value is advanced to a head of the second queue. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A system comprising:
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a memory; a graphics controller; and a chipset coupled between the memory and the graphics controller, the chipset including a memory controller to ensure data coherency through a flush command and to prevent reordering of a first memory access command ahead of a second memory access command previously issued by the graphics controller, the memory controller having a command interface including; a first queue to enqueue the flush command, a second queue to enqueue a synchronization value, and a queue advance circuit to delay the flush command from being dequeued from the first queue until the synchronization value is advanced to a head of the second queue and the flush command is advanced to a head of the first queue. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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Specification