Generating an error signal when accessing an invalid memory page

• US 5,990,914 A
• Filed: 09/09/1997
• Issued: 11/23/1999
• Est. Priority Date: 09/09/1997
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Elliott, Robert C., Lester, Robert Allan, Jones, Phillip M., Santos, Gregory N., Horan, Ronald T.
• Primary Examiner(s): Kim, Matthew M.
• Assistant Examiner(s): Luu, Sy D.
• Application Number:
  US08/926,425
• Time in Patent Office: 805 Days
• Field of Search: 345/503, 345/520-521, 345/514, 345/522, 345/526, 345/515, 345/516, 345/507, 345/509, 711/205-207, 711/112, 395/306-309, 395/310
• US Class Current: 345/531
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units

Abstract

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. One of the feature flags is used as a Present Bit for a corresponding memory page. When the feature flag Present Bit is set, the memory page has been reserved in the physical memory for graphics data and an address translation may be carried out. When the feature flag Present Bit is clear, the memory page has not been reserved for graphics data in the physical memory and a determination must then be made whether to perform the translation or generate an error signal to the computer processor.

Claims

1. A computer system, comprising:

a system processor executing software instructions and generating graphics data;

a system memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of said plurality of bytes of storage has a unique address;

said software instructions and said graphics data being stored in some of said plurality of bytes of storage of said system memory, wherein said graphics data is stored in a plurality of pages of graphics data, each of said plurality of pages of graphics data comprising a number of said plurality of bytes of storage;

an accelerated graphics port (AGP) processor generating video display data from said graphics data and adapted for connection to a video monitor to display said video display data;

a first interface logic for connecting said system processor to said system memory;

a second interface logic adapted for connecting said system processor and said system memory to input-output devices;

a third interface logic for connecting said system processor and said system memory to said AGP processor;

a graphics address remapping table (GART table) having a plurality of entries, each of said plurality of GART table entries comprising an address pointer to a first byte address of a corresponding one of said plurality of pages of graphics data and a present bit for determining if said corresponding one of said plurality of pages of graphics data has been reserved for graphics data; and

said third interface logic reading selected ones of said plurality of GART table entries, wherein said third interface logic determines from said present bit in each one of said selected ones of said plurality of GART table entries if said corresponding one of said plurality of pages of graphics data has been reserved for graphics data;

wherein,

if said corresponding one of the plurality of pages of graphics data has been reserved for graphics data then said third interface logic performs a transaction with said system memory; and

if said corresponding one of the plurality of pages of graphics data has not been reserved for graphics data then said third interface logic generates a system error signal.

2. The computer system of claim 1, wherein said present bit is set to a first logical level when said corresponding one of said plurality of pages of graphics data has been reserved for graphics data.

3. The computer system of claim 2, wherein said first logic level is a logic one.

4. The computer system of claim 2, wherein said first logic level is a logic zero.

5. The computer system of claim 1, wherein said present bit is cleared to a second logical level when said corresponding one of the plurality of pages of graphics data has not been reserved for graphics data.

6. The computer system of claim 5, wherein said second logic level is a logic zero.

7. The computer system of claim 5, wherein said second logic level is a logic one.

8. The computer system of claim 1, wherein software instructions of an application programming interface causes said system processor to reserve said corresponding ones of said plurality of pages of graphics data for graphics data.

9. The computer system of claim 8, wherein said applications programming interface is a GART miniport driver.

10. The computer system of claim 1, where said third interface logic comprises:

a capabilities register having a valid bit error reporting supported bit to indicate when set, that said third interface logic is capable of generating a system error signal if said present bit of said selected one of said plurality of GART table entries is not set and said corresponding one of said plurality of pages of graphics data is accessed by said third interface logic;

a feature control register having a valid bit error reporting enable bit to indicate when set, that said third interface logic will generate said system error signal when said present bit of said selected one of said plurality of GART table entries is not set and said corresponding one of said plurality of pages of graphics data is accessed by said third interface logic; and

a feature status register having a valid bit error detected bit to indicate when set, that said present bit of said selected one of said plurality of GART table entries is not set and when said corresponding one of said plurality of pages of graphics data is accessed by said third interface logic said system error signal will be generated.

11. The computer system of claim 1, where said GART table is stored in said system memory.

12. A computer system having a core logic chipset which connects a computer processor and memory to an accelerated graphics port (AGP), said system comprising:

a central processing unit connected to a host bus;

a random access memory connected to a random access memory bus;

a core logic chipset connected to the host bus and the random access memory bus;

said core logic chipset configured as a first interface bridge between the host bus and the random access memory bus;

said core logic chipset configured as a second interface bridge between the host bus and an accelerated graphics port (AGP) bus; and

said core logic chipset configured as a third interface bridge between the random access memory bus and the AGP bus;

wherein,

said core logic chipset uses a graphics address remapping table (GART table) having a plurality of entries stored in said random access memory, each of the plurality of GART table entries comprising an address pointer to a corresponding one of a plurality of pages of graphics data stored in said random access memory and a present bit for determining if the corresponding one of the plurality of pages has been reserved as graphics data; and

said core logic chipset reads the selected ones of the plurality of GART table entries stored in said random access memory, wherein said core logic chipset determines from said present bit in each one of the selected ones of the plurality of GART table entries if the corresponding one of the plurality of pages has been reserved for graphics data;

wherein,

if the corresponding one of the plurality of pages has been reserved for graphics data then said core logic chipset performs a transaction with said random access memory; and

if the corresponding one of the plurality of pages has not been reserved for graphics data then said core logic chipset generates a system error signal.

13. The computer system of claim 12, further comprising:

a fourth interface bridge between the host bus and a first peripheral component interconnect bus; and

a fifth interface bridge between the random access memory bus and the first peripheral component interconnect bus.

14. The computer system of claim 12, wherein the central processing unit is a plurality of central processing units.

15. The computer system of claim 12, wherein the plurality of pages of graphics data are stored in said random access memory in a non-contiguous and random order.

16. The computer system of claim 15, wherein each of the plurality of GART table entries comprises a plurality of binary bits wherein a first number of most significant bits of the plurality of binary bits represents the address pointer which contains a base address of the corresponding one of the plurality of pages of graphics data.

17. The computer system of claim 16, wherein a bit of a second number of least significant bits of the plurality of binary bits comprises the present bit for each corresponding one of the plurality of pages of graphics data.

18. The computer system of claim 12, wherein the plurality of GART table entries are stored in at least one page of said random access memory.

19. The computer system of claim 12, wherein each of the plurality of pages of graphics data is 4096 bytes.

20. The computer system of claim 12, wherein said core logic chipset is at least one integrated circuit.

21. The computer system of claim 20, wherein the at least one integrated circuit core logic chipset is at least one application specific integrated circuit.

22. The computer system of claim 20, wherein the at least one integrated circuit core logic chipset is at least one programmable logic array integrated circuit.

23. The computer system of claim 12, wherein said central processing unit executes software instructions and generates the graphics data.

24. The computer system of claim 12, further comprising a graphics processor for generating video display data based upon the graphics data.

25. The computer system of claim 24, further comprising a local frame buffer memory coupled to said graphics processor, wherein said graphics processor combines video data stored in said local frame buffer memory with the corresponding ones of the plurality of pages of graphics data read from said random access memory based upon the selected ones of the plurality of GART table entries stored in said cache memory to generate video display data.

26. The computer system of claim 12, further comprising a cache memory to store the selected ones of the plurality of GART table entries prefetched by said core logic chipset from said random access memory.

27. The computer system of claim 12, further comprising a network interface card, a hard disk, a floppy disk drive, a modern, a keyboard, and a mouse.

28. The computer system of claim 12, further comprising a serial port, a parallel port, a keyboard and a real time clock.

29. The computer system of claim 12, further comprising a read only memory basic input-output system (ROM BIOS), a non-volatile random access memory (NVRAM), a tape drive and a CD ROM drive.

30. A method, in a computer system, of determining if pages in the computer system main memory have been reserved for graphics data by examining a present bit of selected ones of a plurality of graphics address remapping table (GART table) entries and then deciding whether to access the pages or generate a system error signal, said method comprising the steps of:

storing a plurality of pages of graphics data in any order in a main memory of a computer system;

storing a graphics address remapping table (GART table) having a plurality of entries in the main memory, each of the plurality of GART table entries comprising an address pointer to corresponding ones of the plurality of pages of graphics data stored in the main memory and a present bit indicating whether the corresponding ones have been reserved for graphics data;

reading a selected one of the plurality of GART table entries stored in the main memory;

determining if the present bit is set in the selected one of the plurality of GART table entries read from the main memory; and

generating a system error signal if the present bit is not set;

otherwise,

accessing the corresponding one of the plurality of pages of graphics data stored in the main memory if the present bit is set.

31. The method of claim 30, further comprising the step of reading the plurality of pages of graphics data in an order determined by the order of the plurality of GART table entries.

32. The method of claim 30, wherein a main memory address is determined for each byte of graphics data stored in the corresponding one of the plurality of pages of graphics data by the base address stored in the one of the plurality of GART table entries and an offset address added to the base address.

33. The method of claim 30, further comprising the step of setting the present bit of at least one of the plurality of GART table entries by an application programming interface.

34. The method of claim 33, further comprising the step of reading the present bit of the at least one of the plurality of GART table entries by the application programming interface.

35. The method of claim 30, further comprising the step of allocating memory locations in the main memory during computer system initialization for storing the plurality of GART table entries.

36. The method of claim 30, wherein the step of reading a selected one is the step of reading a plurality of selected ones.

37. The method of claim 30, further comprising the step of reading a capabilities register having a valid bit error reporting supported bit to determine if a system error signal can be generated when the present bit is not set and the corresponding one of the plurality of graphics data pages is accessed.

38. The method of claim 37, further comprising the step of reading a feature control register having a valid bit error reporting enable bit to indicate when set, that a system error signal can be generated when the present bit of the selected one of the plurality of GART table entries is not set and the associated one of the plurality of pages is accessed.

39. The method of claim 38, further comprising the step of reading a feature status register having a valid bit error detected bit to indicate when set, that the present bit of the selected one of the plurality of GART table entries is not set and when the associated one of the plurality of pages is accessed the system error signal will be generated.

40. The method of claim 30, wherein the system error signal generates a processor non-maskable interrupt.

41. The method of claim 30, further comprising the step of generating video display data with a graphics processor by the graphics processor reading the corresponding ones of the plurality of graphics data pages in a contiguous graphics device address space.

42. A core logic chipset adapted for connecting a computer processor and memory to an accelerated graphics port (AGP) bus, comprising:

an accelerated graphics port (AGP) request queue;

an AGP reply queue;

an AGP data and control logic;

an AGP arbiter;

a memory interface and control logic adapted for connection to a computer system random access memory; and

a host bus interface adapted for connection to a computer system host bus having at least one central processing united connected thereto;

wherein,

said AGP request and reply queues are connected to said memory interface and control logic;

said AGP data and control logic is connected to said memory and interface control logic;

said AGP data and control logic is connected to a host bus interface;

said AGP data and control logic and said AGP arbiter adapted for connection to an AGP bus having an AGP device;

wherein,

said AGP data and control logic is adapted to use a graphics address remapping table (GART table) having a plurality of entries, each of the plurality of entries comprising an address pointer to a corresponding one of a plurality of pages of graphics data stored in the computer system random access memory and a present bit for determining if the corresponding one of the plurality of pages has been reserved for graphics data; and

said AGP data and control logic is adapted to read the selected ones of the plurality of GART table entries stored in the computer system random access memory, wherein said AGP data and control logic determines from said present bit in each one of the selected ones of the plurality of GART table entries if the corresponding one of the plurality of pages has been reserved for graphics data;

wherein,

if the corresponding one of the plurality of pages has been reserved as graphics data then said AGP data and control logic is adapted to perform a transaction with the computer system random access memory; and

if the corresponding one of the plurality of pages has not been reserved as graphics data then said AGP data and control logic is adapted to generate a system error signal.

43. The core logic chipset of claim 42, further comprising:

a host to peripheral component interconnect (PCI) bridge;

a PCI to PCI bridge;

PCI data and control logic;

said host to PCI bus bridge is connected to said host bus interface and is adapted for connection to a PCI bus;

said PCI to PCI bridge is adapted for connect between the AGP bus and PCI bus, wherein said PCI to PCI bridge transfers PCI information transactions between the PCI bus and the AGP bus.

44. The core logic chipset of claim 42, wherein said PCI to PCI bridge comprises a command register having a system error signal enable that controls the bridging of the system error signal detection from said AGP bus to said PCI bus.

45. The core logic chipset of claim 42, wherein said AGP data and control logic comprises a GART capabilities register having a valid bit error reporting supported bit that when set, said AGP data and control logic is capable of generating a system error signal when said AGP device causes an access to the corresponding one of the plurality of pages that has not been reserved for graphics data.

46. The core logic chipset of claim 42, wherein said AGP data and control logic comprises a GART feature control register having a valid bit error reporting enable bit that when set, said AGP data and control logic is adapted to generate a system error signal when said AGP device causes an access to the corresponding one of the plurality of pages that has not been reserved for graphics data.

47. The core logic chipset of claim 42, wherein said AGP data and control logic comprises a GART feature status register having a valid bit error detected bit that when set, said AGP data and control logic has generated a system error signal.