Power amplifier with multiple, switched output stages, and method and driver for driving the output stages using different pattern signals groups

• US 5,991,179 A
• Filed: 02/27/1998
• Issued: 11/23/1999
• Est. Priority Date: 03/10/1997
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Schweighofer, Peter
• Primary Examiner(s): Riley, Shawn
• Application Number:
  US09/032,756
• Time in Patent Office: 634 Days
• Field of Search: 307/82, 307/77, 363/71
• US Class Current: 363/71
• CPC Class Codes: G01R 33/3852 Gradient amplifiers; means for controlling the application of a gradient magnetic field to the sample, e.g. a gradient signal synthesizer
• CPC Class Codes: H03F 3/2178 using more than one switch or switching amplifier in parallel or in series H03F3/2173, H03F3/2175 take precedence
• CPC Class Codes: H03K 17/0812 by measures taken in the control circuit
• CPC Class Codes: H03K 17/64 having inductive loads
• CPC Class Codes: H03K 17/661 connected to both load terminals

Abstract

In a power amplifier having multiple, switched output stages and a driver, and method for driving the switched output stages, a number of drive signal groups are generated for respectively driving the switched output stages. A number of pattern signal groups are generated dependent on at least one input signal, and drive signal groups are generated from the pattern signal groups, with each pattern signal group being allocated respectively to one of the switched output stages, and this allocation is changed in segments. A good load balancing between the individual switched output stages is achieved with a low circuit-oriented outlay.

Claims

1. A method for operating a power amplifier having a plurality of switched output stages, comprising the steps of:

providing at least one input signal to said power amplifier and generating a plurality of pattern signal groups dependent on said at least one input signal, said plurality of pattern signal groups being equal to the plurality of output stages;

generating a plurality of drive signal groups from said pattern signal groups by initially allocating said pattern signal groups respectively to said output stages and changing the allocation of the respective pattern signal groups to the respective output stages in segments by identifying times at which pattern signal groups which will be affected by the change in allocation are compatible with each other and chancing the allocation only at said times; and

respectively driving the plurality of output stages with the plurality of drive signal groups.

2. A method as claimed in claim 1 wherein each pattern signal group comprises a plurality of individual pattern signals, and comprising the additional step of identifying said pattern signal groups as being compatible when pairs of the respective individual pattern signals in the pattern signal groups affected by the change in allocation have coinciding values at said times.

3. A method as claimed in claim 1 comprising the additional steps of:

defining said times synchronously with a switching clock; and

if the pattern signal groups which will be affected by said change in allocation are not compatible at a time defined by said switching clock, delaying a change in allocation until the pattern signal groups which will be affected by said change in allocation are compatible.

4. A method as claimed in claim 1 wherein the step of changing the allocation in segments comprises, upon each allocation change, permutating said allocation of said pattern signal groups respectively to said output stages.

9. A method as claimed in claim 1 wherein each of said pattern signal groups comprises a plurality of pattern signals, and wherein each pattern signal in said plurality of pattern signals is a digital signal.

10. A method as claimed in claim 1 wherein each of said drive signal groups comprises a plurality of drive signals, and wherein each drive signal in said plurality of drive signals is a digital signal.

11. A method as claimed in claim 1 wherein each of said pattern signal groups comprises a plurality of pattern signals and wherein each of said drive signal groups comprises a plurality of drive signals, and wherein each pattern signal in said plurality of pattern signals is a digital signal and wherein each drive signal in said plurality of drive signals is a digital signal.

5. A method for operating a power amplifier having two switched output stages, comprising the steps of:

providing at least one input signal to said power amplifier and generating two pattern signal groups dependent on said at least one input signal, said plurality of pattern signal groups being equal to the plurality of output stages;

generating a plurality of drive signal groups from said pattern signal groups by initially allocating said pattern signal groups respectively to said output stages and changing the allocation of the respective pattern signal groups to the respective output stages in segments by successively interchanging the allocation of said two pattern signal groups to said two output stages; and

respectively driving the plurality of output stages with the plurality of drive signal groups.

15. A method as claimed in claim 5 comprising the additional steps of:

defining said times synchronously with a switching clock; and

if the pattern signal groups which will be affected by said change in allocation are not compatible at a time defined by said switching clock, delaying a change in allocation until the pattern signal groups which will be affected by said change in allocation are compatible.

16. A method as claimed in claim 5 wherein each of said pattern signal groups comprises a plurality of pattern signals, and wherein each pattern signal in said plurality of pattern signals is a digital signal.

17. A method as claimed in claim 5 wherein each of said drive signal groups comprises a plurality of drive signals, and wherein each drive signal in said plurality of drive signals is a digital signal.

18. A method as claimed in claim 5 wherein each of said pattern signal groups comprises a plurality of pattern signals and wherein each of said drive signal groups comprises a plurality of drive signals, and wherein each pattern signal in said plurality of pattern signals is a digital signal and wherein each drive signal in said plurality of drive signals is a digital signal.

6. A method for operating a power amplifier having three switched output stages, comprising the steps of:

providing at least one input signal to said power amplifier and generating three pattern signal groups dependent on said at least one input signal, said plurality of pattern signal groups being equal to the plurality of output stages;

generating a plurality of drive signal groups from said pattern signal groups by initially allocating said pattern signal groups respectively to said output stages and changing the allocation of the respective pattern signal groups to the respective output stages in segments by changing an allocation of one of said three pattern signal groups to one of said three switched output stages at each allocation change; and

respectively driving the plurality of output stages with the plurality of drive signal groups.

14. A method as claimed in claim 6 wherein each pattern signal group comprises a plurality of individual pattern signals, and comprising the additional step of identifying said pattern signal groups as being compatible when pairs of the respective individual pattern signals in the pattern signal groups affected by the change in allocation have coinciding values at said times.

19. A method as claimed in claim 6 wherein each pattern signal group comprises a plurality of individual pattern signals, and comprising the additional step of identifying said pattern signal groups as being compatible when pairs of the respective individual pattern signals in the pattern signal groups affected by the change in allocation have coinciding values at said times.

20. A method as claimed in claim 6 comprising the additional steps of:

defining said times synchronously with a switching clock; and

if the pattern signal groups which will be affected by said change in allocation are not compatible at a time defined by said switching clock, delaying a change in allocation until the pattern signal groups which will be affected by said change in allocation are compatible.

21. A method as claimed in claim 6 wherein each of said pattern signal groups comprises a plurality of pattern signals, and wherein each pattern signal in said plurality of pattern signals is a digital signal.

22. A method as claimed in claim 6 wherein each of said drive signal groups comprises a plurality of drive signals, and wherein each drive signal in said plurality of drive signals is a digital signal.

23. A method as claimed in claim 6 wherein each of said pattern signal groups comprises a plurality of pattern signals and wherein each of said drive signal groups comprises a plurality of drive signals, and wherein each pattern signal in said plurality of pattern signals is a digital signal and wherein each drive signal in said plurality of drive signals is a digital signal.

7. A method for operating a power amplifier having a plurality of switched output stages comprising the steps of:

providing at least one input signal to said power amplifier and generating a plurality of pattern signal groups dependent on said at least one input signal, said plurality of pattern signal groups being equal to the plurality of output stages;

generating a plurality of drive signal groups, each comprising a plurality of drive signals, from said pattern signal groups by initially allocating said pattern signal groups respectively to said output stages and changing the allocation of the respective pattern signal groups to the respective output stages in segments; and

respectively driving the plurality of output stages with the plurality of drive signal groups by employing said drive signals to activate switch elements within the respective output stages.

24. A method as claimed in claim 7 wherein each pattern signal group comprises a plurality of individual pattern signals, and comprising the additional step of identifying said pattern signal groups as being compatible when pairs of the respective individual pattern signals in the pattern signal groups affected by the change in allocation have coinciding values at said times.

25. A method as claimed in claim 7 comprising the additional steps of:

defining said times synchronously with a switching clock; and

if the pattern signal groups which will be affected by said change in allocation are not compatible at a time defined by said switching clock, delaying a change in allocation until the pattern signal groups which will be affected by said change in allocation are compatible.

26. A method as claimed in claim 7 wherein each of said pattern signal groups comprises a plurality of pattern signals, and wherein each pattern signal in said plurality of pattern signals is a digital signal.

8. A method for operating a power amplifier having a plurality of switched output stages, comprising the steps of:

providing at least one input signal to said power amplifier and generating a plurality of pattern signal groups dependent on said at least one input signal, said plurality of pattern signal groups being equal to the plurality of output stages;

generating a plurality of drive signal groups from said pattern signal groups by initially allocating said pattern signal groups respectively to said output stages and changing the allocation of the respective pattern signal groups to the respective output stages in segments and uniquely generating one of said drive signal groups from only one of said pattern signal groups so that, between the changes in allocation, each pattern signal group has a drive signal curve which agrees with a signal curve of only one drive signal group; and

respectively driving the plurality of output stages with the plurality of drive signal groups.

27. A method as claimed in claim 8 wherein each pattern signal group comprises a plurality of individual pattern signals, and comprising the additional step of identifying said pattern signal groups as being compatible when pairs of the respective individual pattern signals in the pattern signal groups affected by the change in allocation have coinciding values at said times.

28. A method as claimed in claim 8 comprising the additional steps of:

defining said times synchronously with a switching clock; and

if the pattern signal groups which will be affected by said change in allocation are not compatible at a time defined by said switching clock, delaying a change in allocation until the pattern signal groups which will be affected by said change in allocation are compatible.

29. A method as claimed in claim 8 wherein each of said pattern signal groups comprises a plurality of pattern signals, and wherein each pattern signal in said plurality of pattern signals is a digital signal.

30. A method as claimed in claim 8 wherein each of said drive signal groups comprises a plurality of drive signals, and wherein each drive signal in said plurality of drive signals is a digital signal.

31. A method as claimed in claim 8 wherein each of said pattern signal groups comprises a plurality of pattern signals and wherein each of said drive signal groups comprises a plurality of drive signals, and wherein each pattern signal in said plurality of pattern signals is a digital signal and wherein each drive signal in said plurality of drive signals is a digital signal.

12. A power amplifier comprising:

a plurality of switched output stages;

means responsive to at least one input signal for generating a plurality of pattern signal groups dependent on said at least one input signal, said plurality of pattern signal groups being equal to the plurality of output stages;

means for generating a plurality of drive signal groups from said pattern signal groups by initially allocating said pattern signal groups respectively to said output stages and changing the allocation of the respective pattern signal groups to the respective output stages in segments; and

means for driving the plurality of output stages with the plurality of drive signal groups.

13. A drive circuit for operating a power amplifier having a plurality of switched output stages, comprising:

means responsive to at least one input signal for generating a plurality of pattern signal groups dependent on said at least one input signal, said plurality of pattern signal groups being equal to the plurality of output stages; and

means for generating a plurality of drive signal groups from said pattern signal groups to drive said output stages by initially allocating said pattern signal groups respectively to said output stages and changing the allocation of the respective pattern signal groups to the respective output stages in segments.