Semiconductor memory device having data protection feature

• US 5,991,197 A
• Filed: 03/24/1998
• Issued: 11/23/1999
• Est. Priority Date: 10/17/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Honma, Tsuyoshi, Kobayashi, Kazuo, Ogura, Taku, Ohba, Atsushi
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Ho, Hoai V.
• Application Number:
  US09/046,583
• Time in Patent Office: 609 Days
• Field of Search: 365/185.11, 365/185.04, 365/195
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells

Abstract

A reset power down mode designating signal and first and second write protect signals are provided to a control circuit. According to the states of these external control signals, the status of unconditional inhibition, unconditional permission, and lock bit (LB) dependency for the protect status of data rewrite is set for each memory block group of a memory array. Therefore, the write protect status can be set in a flexible manner for a nonvolatile semiconductor memory device.

Claims

1. A semiconductor memory device comprising:

a plurality of memory block regions, each memory block region including at least one memory block for storing data in a nonvolatile manner, each memory block region storing data of a different attribute;

control circuitry for setting data rewriting protection status for said plurality of memory block regions on a region-by-region basis according to states of a plurality of external control signals, so that the protection status of one of said memory block regions can be made different from the protection status of another of said memory block regions.

2. The semiconductor memory device according to claim 1, further comprising means corresponding to each of the memory blocks, for storing a lock bit indicating a state of inhibition or permission of rewriting of data stored in a corresponding memory block,

wherein said control circuitry comprises means for determining whether a corresponding lock bit is to be made valid or invalid on the region-by-region basis according to the states of said plurality of external control signals.

3. The semiconductor memory device according to claim 1, wherein said plurality of external control signals include a reset power down mode designating signal that designates a power down mode for reducing consumed current, and first and second write protect designating signals for designating absence and presence of protect for data rewriting.

4. The semiconductor memory device according to claim 1, wherein said data rewriting includes erasure of stored data, and programming and storage of external data.

5. The semiconductor memory device according to claim 1, further comprising a lock bit storage section for storing lock bits for respective memory blocks, a lock bit indicating whether data rewriting of a corresponding memory block is allowed, and

wherein said control circuitry includes a decoder for decoding the external control signals to generate a protect control signal indicating the protect status for the memory block regions on a regional basis,

a region determinator operative according to a block address signal specifying a memory block, for identifying a memory block region including a specified memory block by said block address signal,

a lock determinator for determining the write protect status of the specified memory block in accordance with said protect control signal and an output signal of said region determinator, to selectively make a lock bit for the specified memory block valid or invalid, and to force the lock bit into one of a locking state prohibiting data rewriting when the lock bit is made invalid, in accordance with a result of determination, and

a write control circuit for controlling a data rewriting operation for the specified memory block in accordance with the lock bit received from the lock determinator.

6. The semiconductor memory device according to claim 1, further comprising a lock bit storage section for storing lock bits for respective memory blocks, a lock bit indicating whether data rewriting of a corresponding memory block is allowed, and

wherein said control circuitry includes:

a decoder for decoding the external control signals to generate protect control signals indicating the protect status for the respective memory block regions,

a region determinator operative according to a block address signal specifying a memory block, for identifying a memory block region including a specified memory block by the block address signal,

a selector operative according to an output signal of the region determinator for selecting a protect control signal for the memory block region identified by the region determinator among the protect control signals from the decoder,

a lock determinator for determining the write protect status of the specified memory block in accordance with said control signal and an output signal of said region determinator, to selectively make a lock bit for the specified memory block valid or invalid, and to force the lock bit into one of a locking state prohibiting data rewriting and an unlocking state permitting data rewriting when the lock bit is made invalid, in accordance with a result of determination, and

a rewrite control circuit for controlling a data rewriting operation for the specified memory block in accordance with the lock bit received from the lock determinator.

7. A semiconductor memory device including a plurality of nonvolatile memory blocks, and having a write protect feature, comprising:

lock bit storage sections corresponding respectively to said plurality of nonvolatile memory blocks, for storing lock bits indicating whether data rewriting of corresponding memory blocks is allowed;

first and second write protect designating signal input pins, so that a write protect state of each of said plurality of nonvolatile memory blocks can be set on a region by region basis, the region including at least one memory block, through signals applied to the first and second write protect designating signal pins, the write protect state including a first mode in which allowance of data rewriting of a memory block is determined in accordance with a value of a corresponding lock bit and a second mode in which allowance of data rewriting of the memory block is determined regardless of the value of the corresponding lock bit.

8. A semiconductor memory device, comprising:

a plurality of memory block regions each including at least one memory block for storing data in a nonvolatile manner;

a plurality of lock bit storage circuits provided corresponding to respective memory blocks of said plurality of memory block regions, for storing lock bits indicating whether corresponding memory blocks are allowed to rewrite storage data;

mode setting circuitry for setting write protect status for the memory blocks on a region by region basis in accordance with a combination of states of a plurality of external control signals;

protect control circuitry responsive to a data rewriting operation mode instructing signal for determining whether data rewriting of an addressed memory block is allowed in accordance with a block address signal addressing the addressed memory block, a value of a lock bit for the addressed memory block and an output signal of said mode setting circuitry.

9. The semiconductor memory device according to claim 8, wherein said plurality of external control signals includes a reset power down mode signal, a first write protect signal, and a second write protect signal.