Split sense amplifier and staging buffer for wide memory architecture

• US 5,991,209 A
• Filed: 04/11/1997
• Issued: 11/23/1999
• Est. Priority Date: 04/11/1997
• Status: Expired due to Term

• Current Assignee: Foothills IP LLC
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Chow, Lap-Wai
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US08/827,856
• Time in Patent Office: 956 Days
• Field of Search: 365/189.05, 365/205, 365/208, 365/190
• US Class Current: 365/189.05
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

In an amplifier design for a wide memory architecture, a staging buffer can be integrated with the final stage of a multi-stage sense amplifier. The staging buffer includes a memory latch for storing at least one bit of data. The data is transferred into the staging buffer from memory upon strobing at least one read enable line, and transferred from the staging buffer to a data bus upon strobing at least one write enable line. The data signal is transferred from the memory to the staging buffer at a voltage level lower than the full swing voltage level. The memory architecture produced using this design technique allows for a much lower voltage swing on all of the data lines, thus lowering the power requirements of the circuit.

Claims

1. A memory architecture comprising:

a memory for storing an array of data at a first voltage level;

a first amplifier stage connected to the memory, the first amplifier stage including a pair of cross-connected transistors with an equalization transistor connected therebetween, the first amplifier stage having a pair of complimentary data input lines and a pair of complimentary data output lines, the first amplifier stage further having a pair of signal driving transistors, wherein each of the data input lines is connected to one of the signal driving transistors, and the output of each signal driving transistor is connected to one of the cross-connected transistors, the first amplifier stage receiving a data signal from the memory at the first voltage level and increasing the voltage level of the data signal to a second voltage level;

a plurality of second amplifier stages connected to the first amplifier stage, each of the second amplifier stages having a data input line, a complementary data input line, and a data output line, each of the second amplifier stages further including a memory latch for receiving the data signal from the first amplifier stage and storing at least one bit of data upon strobing at least one read enable line, and writing said data to an output data bus upon strobing at least one write enable line, each of the second amplifier stages receiving the data signal from the first amplifier stage at the second voltage level and increasing the voltage level of the data signal to a buffer voltage level; and

a common data bus connecting the first amplifier stage with the plurality of second amplifier stages, wherein the data signal is transferred across the data bus from the first amplifier stage to one of the second amplifier stages at the second voltage level, and wherein the first voltage level and the second voltage level are substantially lower than the buffer voltage level.

2. The memory architecture of claim 1 wherein said memory latch further includes a first pair of cross-connected transistors connected to a second pair of cross-connected transistors.

3. The memory architecture of claim 2 wherein said second amplifier stage includes a read enable transistor connected between said data input line of said second amplifier stage and said first and second pair of cross-connected transistors.

4. The memory architecture of claim 2 wherein said first pair of cross-connected transistors are p-channel MOSFET transistors.

5. The memory architecture of claim 2 wherein said second pair of cross-connected transistors are n-channel MOSFET transistors.

6. The memory architecture of claim 2 wherein said second amplifier stage includes an equalization transistor connected between said first pair of cross-connected transistors.

7. The memory architecture of claim 2 wherein said second amplifier stage includes an equalization transistor connected between said second pair of cross-connected transistors.

8. The memory architecture of claim 1 wherein said second amplifier stage includes an inverter connected between said memory latch and said output data bus.

9. The memory architecture of claim 1 wherein said second amplifier stage includes a buffer connected between said memory latch and said output data bus.

10. A memory architecture comprising:

a memory for storing an array of data at a first voltage level;

a sense amplifier connected to the memory, the sense amplifier including a pair of cross-connected transistors, and an equalization transistor connected therebetween, the first amplifier stage having a pair of complimentary data input lines and a pair of complimentary data output lines, the sense amplifier stage further having a pair of signal driving transistors, wherein each of the data input lines is connected to one of the signal driving transistors, and the output of each signal driving transistor is connected to one of the cross-connected transistors, the sense amplifier receiving a data signal from the memory at the first voltage level and increasing the voltage level of the data signal to a second voltage level;

a pair of staging buffers connected to the sense amplifier, each of the staging buffers having a data input line, a complementary data input line, and a data output line, each of the staging buffers further including a memory latch for receiving the data signal from the sense amplifier and storing at least one bit of data upon strobing at least one read enable line, and writing said data to a vector unit upon strobing a pair of write enable lines, the staging buffers being individually responsive to address decoding circuitry, the staging buffers receiving the data signal from the sense amplifier at the second voltage level and increasing the voltage level of the data signal to a buffer voltage level for temporary storage in the memory latch; and

a common data bus connecting the sense amplifier with the pair of staging buffers, said common data bus including a data line and a complimentary data line, wherein the data signal is transferred across the data bus from the sense amplifier to one of the staging buffers at the second voltage level, and wherein the first voltage level and the second voltage level are substantially lower than the buffer voltage level for reducing a power consumption level of the memory architecture.

11. The memory architecture of claim 10 wherein said memory latch further includes a first pair of cross-connected transistors connected to a second pair of cross-connected transistors.

12. The memory architecture of claim 11 wherein said staging buffers include a pair of read enable transistors connected between said data input lines of said staging buffers and said first and second pair of cross-connected transistors.

13. The memory architecture of claim 11 wherein said staging buffers include an equalization transistor connected between said first pair of cross-connected transistors.

14. The memory architecture of claim 11 wherein said staging buffers include an equalization transistor connected between said second pair of cross-connected transistors.

15. The memory architecture of claim 10 wherein said staging buffers include an inverter connected between said memory latch and said vector unit.

16. The memory architecture of claim 10 wherein said staging buffers include a buffer connected between said memory latch and said vector unit.

17. The memory architecture of claim 10 wherein a single circuit forming each of the staging buffers is used for amplifying and storing the data signal at the buffer voltage level.