Dynamic communication line analyzer apparatus and method
First Claim
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1. A communication line test device comprising:
- ,a plurality of test processors;
at least one line interface to the communication line carrying signals to be tested;
a switch matrix in communication with said test processors and said line interface permitting simultaneous testing by said test processors of said signals, said switch matrix comprising a plurality of logical data selectors which selectively create communications pathways for the exchange of data between said test processors and said line interface, said switch matrix further comprising a field programmable gate array;
memory for storing a logic configuration;
a microprocessor connected to said memory and said field programmable gate array for loading said logic configuration into said field programmable gate array; and
a display system connected to said microprocessor for creating and choosing said logic configuration.
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Abstract
A novel high speed telecommunications testing apparatus and method which utilizes field programmable gate arrays to produce dynamic test modules for DS1, DS3, SONET and ATM signals interconnected by a high speed switching fabric. The high speed switch permits the direct exchange of signals from one test module to another thereby permitting simultaneous testing of different communications line protocols and further provides for multiple tests on a single data stream. Individual line interfaces are provided for DS1, DS3, and SONET lines which terminate and frame incoming and outgoing signals. Data exchange between modules in accomplished through the high speed switch fabric.
107 Citations
2 Claims
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1. A communication line test device comprising:
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a plurality of test processors; at least one line interface to the communication line carrying signals to be tested; a switch matrix in communication with said test processors and said line interface permitting simultaneous testing by said test processors of said signals, said switch matrix comprising a plurality of logical data selectors which selectively create communications pathways for the exchange of data between said test processors and said line interface, said switch matrix further comprising a field programmable gate array; memory for storing a logic configuration; a microprocessor connected to said memory and said field programmable gate array for loading said logic configuration into said field programmable gate array; and a display system connected to said microprocessor for creating and choosing said logic configuration.
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2. A method of testing a communication line utilizing a single instrument setup comprising:
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providing an interface to a line carrying a first protocol signal; extracting a second protocol signal embedded within said first protocol signal; and simultaneously performing analysis on said first protocol signal and said second protocol signal.
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Specification
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Current AssigneeDigital Lightwave Incorporated
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Original AssigneeDigital Lightwave Incorporated
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InventorsMyers, Kenneth T., Zwan, Bryan J.
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Primary Examiner(s)Patel, Ajit
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Assistant Examiner(s)Phunkulh, Bob A.
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Application NumberUS09/005,623Time in Patent Office683 DaysField of Search370/241, 370/242, 370/243, 370/244, 370/245, 370/246, 370/247, 370/248, 370/249, 370/250, 371/20.1-20.5, 379/1, 379/4, 379/5, 379/21-23, 379/26-28US Class Current370/249CPC Class CodesH04J 2203/0003 Switching fabrics, e.g. tra...H04J 2203/0062 TestingH04J 3/14 Monitoring arrangements for...H04L 1/24 Testing correct operationH04L 2012/5628 TestingH04L 49/104 Asynchronous transfer mode ...H04Q 11/0478 Provisions for broadband co...
