Digital switch

• US 5,991,295 A
• Filed: 10/07/1996
• Issued: 11/23/1999
• Est. Priority Date: 10/10/1995
• Status: Expired due to Fees

• Current Assignee: Madge Networks Ltd. (Celestica Incorporated)
• Original Assignee: Madge Networks Ltd. (Celestica Incorporated)
• Inventors: Tout, Arthur James Viggo, Johnson, Stephen Mark
• Primary Examiner(s): Horabik, Michael
• Assistant Examiner(s): Harper, Kevin C.
• Application Number:
  US08/729,755
• Time in Patent Office: 1,142 Days
• Field of Search: 370/237, 370/428, 370/429, 370/412, 370/415, 370/416, 370/410, 370/468, 370/418, 370/414, 370/229, 370/375, 370/376, 370/395
• US Class Current: 370/395.7
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04L 49/108 using shared central buffer
• CPC Class Codes: H04L 49/203 ATM switching fabrics with multicast or broadcast capabilities
• CPC Class Codes: H04L 49/255 Control mechanisms for ATM switching fabrics
• CPC Class Codes: H04L 49/257 Cut-through or wormhole routing

Abstract

A switch fabric is provided which comprises a shared memory, a number of switch fabric ports, and a switch fabric data controller. The switch fabric data controller routes blocks of data received at one switch fabric port to one or more other switch fabric ports and writes and reads data to and from, respectively, the shared memory. The switch fabric data controller preferentially routes a block of data from the one switch fabric port to the one or more other switch fabric ports without writing the block of data into the shared memory if the one or more other desired switch fabric ports are free or become free within a predetermined period, and otherwise writes the block of data into the shared memory for temporary storage if the one or more other switch fabric ports are busy. In this manner, the switch fabric facilitates "cut-through" of blocks of data across a switch without the need to write the blocks of data to a shared memory, thereby reducing latency.

Claims

1. A switch fabric comprising:

a shared memory;

a number of switch fabric ports; and

,

a switch fabric data controller for routing blocks of data received at one switch fabric port to one or more other switch fabric ports and writing and reading data to and from, respectively, the shared memory, wherein the switch fabric data controller preferentially routes a block of data from the one switch fabric port to the one or more other switch fabric ports without writing the block of data into the shared memory if the one or more other desired switch fabric ports are free or become free within a predetermined period, and otherwise writes the block of data into the shared memory for temporary storage if the one or more other switch fabric ports are busy.

2. A switch fabric according to claim 1, further comprising at least one traffic concentrator for multiplexing N datastreams for transmission to the switch fabric data controller comprising:

N input ports;

an output port; and

,

means for repeatedly generating N slots having a predetermined length for receiving blocks of data arriving at the input ports and transmitting the blocks of data as a multiplexed datastream at the output port, wherein a slot may initially be exclusively allocated to one input port for transmitting blocks of data received at the input port and subsequently the slot can be re-allocated to another input port when the one input port releases control of the slot.

3. A switch fabric according to claim 2, in which the input buffer of the switch fabric data controller stores blocks of data arriving from at least one traffic concentrator and the switch fabric data controller further comprises a separate output buffer for storing blocks of data to be routed from the switch fabric data controller to one or more of the switch fabric ports.

4. A switch fabric according to claim 3, in which both the input buffer and output buffer are each provided with space sufficient to store two blocks of data for each of the N switch fabric ports.

5. A switch fabric according to claim 4, in which the switch fabric data controller is arranged to hold segments of a block of data received sequentially at the input buffer whilst monitoring the output buffer and if a required location in the output buffer associated with a required switch fabric port becomes free before the entire block of data has been received, transfers the entire block of data to the output buffer.

6. A switch fabric according to claim 5, in which if required location in the output buffer is not free by the time the entire block of data is received at the input buffer, the switch fabric data controller is arranged to write the entire block of data to a queue in the shared memory.

7. A switch fabric according to claim 3, in which the switch fabric data controller includes means for repeatedly generating N slots each having a predetermined length for receiving blocks of data arriving at the output buffer and transmitting the blocks of data as a multiplexed datastream from the output buffer to one or more of the switch fabric ports.

8. A switch fabric according to claim 7, in which each of the N slots is permanently and exclusively allocated to one respective switch fabric port for the transmission of blocks of data from the output buffer to the switch fabric port.

9. A switch fabric according to claim 8, in which the length of each slot generated by the switch fabric data controller is fraction 1/2X of the size of a block of data, where X is a positive integer.

10. A switch fabric according to claim 9, in which the switch fabric further comprises traffic expansion means for demultiplexing the one or more datastreams from the output buffer of the switch fabric data controller ASIC to the switch fabric ports.

11. A switch fabric according to claim 10, in which the traffic concentrator and the traffic expansion means are implemented together on a traffic control ASIC.

12. A switch fabric according to claim 2, in which the length of each slot is a fraction 1/X of the length of a block of data, where X is a positive integer.

13. A switch fabric according to claim 12, in which a plurality traffic concentrators are connected to the switch fabric data controller.

14. A switch fabric according to claim 12, in which the switch fabric includes a shared memory data bus which is sufficiently wide to transfer the same fraction 1/X of the block of data to the shared buffer memory as that transferred by a traffic concentrator in a single slot, where X is a positive integer, and the switch fabric data controller is arranged to write and read blocks of data to and from, respectively, the shared memory on the shared memory data bus.

15. A switch fabric according to claim 14, in which the shared memory comprises two banks, each having a predetermined depth and at least the same width as the shared memory data bus.

16. A switch fabric according to claim 15, in which the switch fabric data controller further comprises an address buffer driven by the switch fabric data controller for holding the value of an address in one bank of the shared memory to allow a segment of data from a block of data held in the input buffer of the switch fabric to be written to that address, and an address latch for latching the address held by the address buffer to enable a successive segment of the block of data held in the input buffer to be written sequentially to the corresponding address in the other bank of the shared memory.

17. An asynchronous transfer mode (ATM) switch comprising:

a back plane;

a microprocessor card connected to said back plane;

at least two port cards connected to said back plane; and

a switch fabric connected to said back plane, said switch fabric comprising;

a shared memory;

a number of switch fabric ports; and

,

a switch fabric data controller for routing blocks of data received at one switch fabric port to one or more other switch fabric ports and writing and reading data to and from, respectively, the shared memory, wherein the switch fabric data controller preferentially routes a block of data from the one switch fabric port to the one or more other switch fabric ports without writing the block of data into the shared memory if the one or more other desired switch fabric ports are free or become free within a predetermined period, and otherwise writes the block of data into the shared memory for temporary storage if the one or more other switch fabric ports are busy.