Integrated multiport switch having independently resettable management information base (MIB)

• US 5,991,305 A
• Filed: 12/18/1997
• Issued: 11/23/1999
• Est. Priority Date: 02/14/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Simmons, Philip, Erimli, Bahadir
• Primary Examiner(s): VU, HUY DUY
• Application Number:
  US08/992,922
• Time in Patent Office: 705 Days
• Field of Search: 370/412, 370/413, 370/414, 370/415, 370/416, 370/417, 370/418, 370/420, 370/229, 370/230, 370/231, 370/402, 370/404, 370/360, 370/363, 370/422, 370/423, 370/424, 370/425 , 370/241, 370/252, 370/445, 379/229, 395/200.3, 395/200.79, 395/200.8
• US Class Current: 370/422
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H04L 12/1863 comprising mechanisms for improved reliability, e.g. status reports arrangements for detecting or preventing errors by carrying supervisory signal the return channel H04L1/16
• CPC Class Codes: H04L 12/4641 Virtual LANs, VLANs, e.g. virtual private networks [VPN] LAN interconnection over a bridge based backbone H04L12/462; encapsulation techniques H04L12/4633; routing of packets H04L45/00; packet switches H04L49/00; virtual private networks for security H04L63/0272
• CPC Class Codes: H04L 12/4645 Details on frame tagging routing of packets H04L45/00; support for virtual LAN H04L49/354
• CPC Class Codes: H04L 12/467 Arrangements for supporting untagged frames, e.g. port-based VLANs
• CPC Class Codes: H04L 41/0213 Standardised network management protocols, e.g. simple network management protocol [SNMP]
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6225 Fixed service order, e.g. Round Robin
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/255 Control mechanisms for ATM switching fabrics
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/3054 Auto-negotiation, e.g. access control between switch gigabit interface connector [GBIC] and link
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/354 for supporting virtual local area networks [VLAN]
• CPC Class Codes: H04L 49/40 : Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: H04L 49/50 : Overload detection or protection within a single switching element
• CPC Class Codes: H04L 49/552 : by ensuring the integrity of packets received through redundant connections
• CPC Class Codes: H04L 49/555 : Error detection
• CPC Class Codes: H04L 49/90 : Buffering arrangements
• CPC Class Codes: H04L 49/901 : using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9047 : including multiple buffers, e.g. buffer pools
• CPC Class Codes: H04L 49/9063 : Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9073 : Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9078 : using an external memory or storage device
• CPC Class Codes: H04L 49/9084 : Reactions to storage capacity overflow
• CPC Class Codes: H04Q 2213/1316 : Service observation, testing
• CPC Class Codes: H04Q 2213/13162 : Fault indication and localisation
• CPC Class Codes: H04Q 3/54591 : Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis

Abstract

An integrated multiport switch (IMS) in which an on-chip management information base (MIB) accumulation processor enables monitoring of a significantly larger number of MIB objects to be stored in external memory while minimizing media access controller (MAC) complexity. A MAC for each port in the IMS outputs a MIB report for each transmission or reception of data according to a specific compressed format to a MIB engine that can be centrally located on the chip. The MIB engine decodes the MIB report into a plurality of associated MIB objects, which are temporarily accumulated until the external memory is updated. The MIB engine initiates the stored MIB value updating process by retrieving the values from the external memory and adding the accumulated MIB objects to the retrieved values. The updated MIB objects are then transmitted back to the external memory for storage therein and the MIB engine object values are cleared. Reset of the MIB related storage elements in response to an external data signal is effected independently of other chip logic elements.

Claims

1. In an integrated multiport network switch comprising an integrated chip having a plurality of ports for transmitting data to and receiving data from a data network, said chip comprising a plurality of storage means, a method comprising the steps of:

accumulating data relating to switch operation in one of said storage means;

repetitively transferring the data accumulated in said accumulating step to a memory external to said chip;

resetting said one storage means independently of the others of said plurality of storage means in response to a reset data signal, said resetting step comprising clearing data stored in said one storage means; and

suspending said accumulating step when said resetting step occurs; and

wherein said data is related to predefined parameters for each transmission of data and reception of data at said ports and said one of said storage means is a component of a management information base (MIB) engine.

2. A method as recited in claim 1, wherein said resetting step further comprises the steps of:

receiving said reset data signal in said MIB engine; and

holding said data signal to temporarily maintain said suspending step.

5. A method as recited in claim 1, further comprising the step of testing chip operation subsequent to said resetting step.

6. A method as recited in claim 2, wherein said held signal contains a predesignated data bit in a first binary state, and further comprising the step of

terminating said suspending step in response to a resume data signal.

7. A method as recited in claim 6, wherein said resume data signal contains said predesignated data bit in a second binary state and said terminating step comprises holding said resume data signal in said MIB engine in replacement of said reset data signal.

8. A method as recited in claim 1, wherein said accumulating step comprises the steps of:

generating said data at each of said ports as transmission or reception activity occurs thereat; and

routing the data generated at each port in said generating step to said MIB engine.

9. A method as recited in claim 1, wherein said step of repetitively transferring comprises:

retrieving data from said external memory;

adding said accumulated to the data retrieved in said retrieving step to obtain updated data; and

replacing data in said external memory with said updated data;

and said resetting step further comprises suspending said step of repetitively transferring.

3. In an integrated multiport network switch comprising an integrated chip having a plurality of ports for transmitting data to and receiving data from a data network, said chip comprising a plurality of storage means, a method comprising the steps of:

accumulating data relating to switch operation in one of said storage means;

repetitively transferring the data accumulated in said accumulating step to a memory external to said chip; and

resetting said one storage means independently of the others of said plurality of storage means in response to a reset data signal;

wherein said reset data signal is generated by a host device external to said chip and applied to a protocol control information (PCI) bus on said chip.

4. In an integrated multiport network switch comprising an integrated chip having a plurality of ports for transmitting data to and receiving data from a data network, said chip comprising a plurality of storage means, a method comprising the steps of:

accumulating data relating to switch operation in one of said storage means;

repetitively transferring the data accumulated in said accumulating step to a memory external to said chip;

resetting said one storage means independently of the others of said plurality of storage means in response to a reset data signal, said resetting step comprising clearing data stored in said one storage means; and

suspending said accumulating step when said resetting step occurs; and

further comprising the step of clearing said external memory while said accumulating step is suspended.

10. An integrated multiport network switch coupled to a data network and having a logic chip comprising:

a plurality of ports for transmitting data to and receiving data from said data network;

a protocol control information (PCI) interface for interfacing said switch with an external host and an external memory;

a plurality of storage means, one of said storage means accumulating data relating to switch operation; and

means for resetting said one storage means independently of the others of said plurality of storage means;

wherein said logic chip further comprises;

a media access controller (MAC) associated with each said port for generating management information base (MIB) data related to predefined parameters for each transmission of data and reception of data at the respective port; and

a management information base (MIB) engine connected to receive MIB data from each of said MACs for accumulating said MIB data in said one storage means.