Adaptive equalization using a minimum- jitter criterion

• US 5,991,339 A
• Filed: 01/16/1998
• Issued: 11/23/1999
• Est. Priority Date: 01/16/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ben-Tal, Rafi, Bazes, Mel
• Primary Examiner(s): Ghebretinsae, Temesghen
• Application Number:
  US09/008,050
• Time in Patent Office: 676 Days
• Field of Search: 375/229, 375/232, 333/18, 708/323
• US Class Current: 375/232
• CPC Class Codes: H03H 11/04 Frequency selective two-port networks
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters

Abstract

An adaptive equalizer is implemented using digital feedback control and using jitter as the adjustment criteria. An adjustable transfer function is implemented to equalize an input signal to enhance the frequency response of the associated system. Jitter is determined for the filtered signal, and the frequency response of the transfer function is varied accordingly by applying a digital adjustment signal to the transfer function structure (for example, a lead-lag filter). The adaptive equalizer can thereby adapt to various transmission medium lengths and signal degradation levels.

Claims

1. An adaptive equalizer, comprising:

a variable filter having an input to receive an input signal and an adjustable transfer function to produce a filtered signal based on the input signal;

a detector coupled to the variable filter to receive the filtered signal and produce a decoded signal based on the filtered signal;

a clock and data recovery unit coupled to the detector to receive the decoded signal and produce a recovered signal based on the decoded signal; and

an adaptation control unit coupled to the clock and data recovery unit to receive the recovered signal, and coupled to the variable filter to provide an adjustment signal according to a determination of jitter of the filtered signal.

2. The adaptive equalizer of claim 1, wherein the adjustment signal is a digital signal.

3. The adaptive equalizer of claim 1, wherein the recovered signal includes a transition data signal, and the transition data signal is provided to the adaptation control unit.

4. The adaptive equalizer of claim 1, wherein the recovered signal includes a clock signal and a data signal.

5. The adaptive equalizer of claim 1, wherein the transfer function has a frequency response characteristic, and is implemented as a filter including a variable resistor.

6. The adaptive equalizer of claim 5, wherein the adjustment signal is applied to specify a resistance value of the variable resistor.

7. The adaptive equalizer of claim 1, wherein the adjustable transfer function has a frequency response characteristic and is implemented as at least one first-order lead-lag filter, and wherein the at least one filter includes a variable resistor, and wherein the adjustment signal is applied to set a resistance value of the variable resistor to affect the frequency response characteristic.

8. The adaptive equalizer of claim 1, wherein the filtered signal is an analog signal, and the decoded signal and the recovered signal are digital signals.

9. The adaptive equalizer of claim 1, wherein the input signal is an MLT-3 signal, the filtered signal is an MLT-3 signal, and the decoded signal is an NRZI signal.

10. The adaptive equalizer of claim 9, wherein the detector performs MLT-3 to NRZI conversion to produce the decoded signal.

11. The adaptive equalizer of claim 1, further comprising a symbol error detector coupled to the clock and data recovery unit to receive the recovered signal and produce a symbol error signal when an error condition exists in the recovered signal.

12. The adaptive equalizer of claim 11, wherein the symbol error detector is coupled to the adaptation control unit to provide the symbol error signal, and wherein the adaptation control unit performs an adaptation process when the symbol error signal is asserted.

13. The adaptive equalizer of claim 1, wherein the variable filter, detector, clock and data recovery unit and adaptation control unit are implemented in a network physical interface device.

14. A method for adaptive equalization, comprising the steps of:

receiving an input signal;

applying a transfer function to the input signal to produce a filtered signal;

decoding the filtered signal to produce a decoded signal;

producing a recovered signal based on the decoded signal;

determining jitter based on the recovered signal;

producing an adjustment signal based on the jitter; and

applying the adjustment signal to the transfer function to cause response adjustment of the transfer function.

15. The method of claim 14, wherein the adjustment signal is a digital signal.

16. The method of claim 14, wherein the input signal and the filtered signal are analog signals, and the decoded signal and the recovered signal are digital signals.

17. The method of claim 14, wherein the recovered signal includes a transition data signal, a clock signal and a data signal.

18. The method of claim 17, wherein the transition data signal includes at least one of transition location information and a number of transitions in each clock period.

19. The method of claim 14, further comprising the step of:

adjusting the transfer function based on a comparison of an equalizer normal operating range to a clock-to-transition ratio of the recovered signal.

20. The method of claim 14, further comprising the step of:

adjusting the transfer function by repeatedly stepping the adjustment signal by one unit until jitter has been minimized.

21. A network physical interface device, comprising:

an input to receive an input signal;

an equalization unit, comprising

a variable filter operatively coupled to the input and including a transfer function having a frequency response characteristic to produce a filtered signal based on the input signal,

a decoding detector operatively coupled to the variable filter to receive the filtered signal and produce a decoded signal based on the filtered signal,

a clock and data recovery unit operatively coupled to the decoding detector to receive the decoded signal and produce a recovered signal, including at least one of a clock signal, a data signal and a transition data signal,

an adaptation control unit operatively coupled to the clock and data recovery unit to receive the recovered signal and produce a digital adjustment signal based on jitter, as determined from the recovered signal, and further coupled to the variable filter to provide the digital adjustment signal,

wherein the digital adjustment signal is applied to the transfer function to adjust the frequency response characteristic of the transfer function; and

an output to output the recovered signal.

22. The network physical interface device of claim 21, wherein the digital adjustment signal is at least two bits wide.

23. The network physical interface device of claim 21, wherein the transfer function includes a variable resistor structure, and the digital adjustment signal is applied to the variable resistor structure to set the resistance level.

24. The network physical interface device of claim 21, wherein the equalization unit further comprises a baseline wander compensation unit.

25. A computer, comprising:

a processor; and

a network interface unit coupled to the processor and including an adaptive equalizer, the adaptive equalizer comprising

a variable filter having an input to receive an input signal and an adjustable transfer function to produce a filtered signal based on the input signal;

a detector coupled to the variable filter to receive the filtered signal and produce a decoded signal based on the filtered signal;

a clock and data recovery unit coupled to the detector to receive the decoded signal and produce a recovered signal based on the decoded signal; and

an adaptation control unit coupled to the clock and data recovery unit to receive the recovered signal, and coupled to the variable filter to provide an adjustment signal according to a determination of jitter of the filtered signal.