Flash EEprom system with cell by cell programming verification

• US 5,991,517 A
• Filed: 12/20/1996
• Issued: 11/23/1999
• Est. Priority Date: 04/13/1989
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Mehrotra, Sanjay, Norman, Robert D.
• Primary Examiner(s): Hua, Ly
• Application Number:
  US08/771,708
• Time in Patent Office: 1,068 Days
• Field of Search: 365/185.22, 365/185.19, 365/189.01, 365/226, 365/201, 395/182.06, 395/182.01
• US Class Current: 714/3
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 : Hybrid storage device
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5621 : using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 : Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 : Erasing circuits
• CPC Class Codes: G11C 16/10 : Programming or data input circuits
• CPC Class Codes: G11C 16/16 : for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3436 : Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/344 : Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 : Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 : Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 : Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 : Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 : Reference cells
• CPC Class Codes: G11C 2211/5643 : Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2216/18 : Flash erasure of all the cells in an array, sector or block simultaneously
• CPC Class Codes: G11C 29/00 : Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/26 : Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/34 : Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/765 : in solid state disks
• CPC Class Codes: G11C 29/82 : for EEPROMs
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement individually verifies the states of a plurality of cells that are being programmed in parallel in order to terminate the programming, as a result of the verification, on a cell-by-cell basis as the cells reach their programmed states.

Claims

1. A method of operating an EEprom system having memory cells that individually include an electrically floating gate carrying a charge level that is alterable in response to appropriate voltage conditions being applied to the cell in order to set a variable threshold level thereof into a range that is determinable by reading the cell, said method comprising:

applying said appropriate voltage conditions in parallel to a plurality of said memory cells, thereby to alter the charge levels on the floating gates of said plurality of memory cells,

determining the threshold level ranges in which individual ones of said plurality of memory cells lie, and

terminating said application of appropriate voltage conditions to individual ones of said plurality of memory cells upon their being determined to have reached desired threshold level ranges while continuing to apply said appropriate voltage conditions to others of said plurality of cells until all of the plurality of cells are determined to have reached their desired threshold level ranges.

2. The method of claim 1, wherein there are exactly two threshold level ranges.

3. The method of claim 1, wherein there are more than two threshold level ranges.

4. The method of claim 1, wherein the threshold level ranges are separated by exactly one breakpoint threshold level, thereby to provide exactly two non-overlapping threshold level ranges.

5. The method of claim 1, wherein the threshold level ranges are separated by more than one breakpoint threshold level, thereby to provide more than two non-overlapping threshold level ranges.

6. The method of claim 1, wherein said desired threshold level ranges include an erased threshold level range.

7. The method of claim 1, wherein the array of memory cells are grouped into blocks of cells wherein the threshold levels of cells within a selected one of the blocks are changed together to a single given threshold level range prior to applying said appropriate voltage conditions in parallel to the plurality of cells within said one block.

8. The method of claim 7, wherein individual ones of said blocks include a specific number of memory cells and said plurality of memory cells to which said appropriate voltage conditions are applied in parallel are less than said specific number, and additionally comprising repeating for another plurality of cells within said one block said applying, determining and terminating operations.

9. The method of claim 7, wherein individual ones of the blocks of cells contain a number of spare cells, and further wherein the spare cells within a particular block are substituted in place of any defective cells within said plurality of cells of said particular block.

10. The method of any one of claims 1-9, carried out on a single integrated circuit chip.

11. The method of claim 1, wherein the array of memory cells are grouped into blocks of cells wherein the threshold levels of cells within individual ones of the blocks are changed together to a single given threshold level range prior to applying said appropriate voltage conditions in parallel to the plurality of cells within one of the blocks, the method further comprising simultaneously changing the threshold levels of cells within a selected two or more blocks to said given level range.

12. The method of claim 1 wherein the desired ones of said threshold level ranges reached by applying appropriate voltage conditions to the plurality of memory cells correspond to a chunk of input data being programmed into the memory system.

13. The method of claim 12, wherein the plurality of cells are determined to have reached the desired threshold level ranges by comparing the threshold levels of the plurality of cells with the chunk of input data.

14. The method of claim 13, wherein the chunk of input data is stored in a cache memory prior to being programmed into memory cells within the EEprom.

15. The method of claim 5, wherein the appropriate voltage conditions are applied to said plurality of memory cells in successive applications of said voltage pulses that individually shift the threshold level of the cells to which the voltage pulses are applied less than one half of a difference between adjacent ones of the breakpoint levels.

16. The method of either of claims 3 or 5, wherein terminating the application of appropriate voltage conditions to individual ones of the plurality of memory cells occurs upon their being determined to have been programmed to within the desired threshold levels by a margin.

17. The method of any one of claims 1, 2 or 4, wherein individual ones of the plurality of memory cells are determined to have reached their desired threshold level ranges by comparison with at least one reference level stored in at least one of the memory cells.

18. The method of either of claims 3 or 5, wherein individual ones of the plurality of memory cells are determined to have reached their desired threshold level ranges by comparison with two or more reference levels stored in two or more of the memory cells.

20. The memory system according to claim 18, wherein the plurality of addressed cells are less than a number of cells within the individual blocks.

19. An electrically erasable and programmable read only memory system, comprising:

an array of electrically alterable memory cells that individually include a field effect transistor having a floating gate and a threshold level that is variable in accordance with an amount of charge carried by the floating gate, said array being divided into blocks of cells that are resettable together, cells within said blocks being addressable for application of programming voltage conditions to individually program them into one of more than two distinct threshold level ranges corresponding to more than one bit of input data per cell,

a reset circuit that simultaneously applies reset voltage conditions to the cells within individual blocks to drive the effective threshold levels of such cells to a reset state,

a programming circuit that applies the programming voltage conditions to a plurality of addressed cells within a reset block to drive the effective threshold voltage of the addressed cells toward one of the more than two programmable threshold level ranges,

a reading circuit that monitors in parallel the threshold level ranges of the plurality of addressed cells, and

a control circuit that individually terminates application of the programming voltage conditions to any one of the plurality of addressed cells when the reading circuit verifies that said any one cell has reached the programmable threshold level range that corresponds to the input data being stored therein, while enabling further application of the programming voltage conditions to others of the plurality of addressed cells that have not yet been so verified, until all of the plurality of addressed cells are verified.

21. The memory system according to claim 19, wherein the control circuit includes a plurality of latches and means for setting individual ones of the latches in response to corresponding ones of said plurality of addressed cells being verified.

22. The memory system according to claim 19, wherein said more than two distinct threshold level ranges are non-overlapping and separated from each other by two or more breakpoint threshold levels.

23. The memory system according to claim 22, wherein the reading circuit includes means for ascertaining the individual threshold level ranges of the plurality of memory cells after the cells have been programmed into the individual threshold level ranges beyond one of their breakpoints by a margin.

24. The memory system according to claim 19, wherein the programming circuit causes the plurality of addressed cells to be programmed with successive applications of said programming voltage conditions, and the reading circuit operates to monitor the threshold level ranges of the plurality of addressed cells in between applications of said programming voltage conditions.

25. The memory system according to claim 24, wherein the programming circuit further shifts the threshold levels of the individual addressed cells by less than one half of a difference between at least two breakpoint threshold levels defining one of the threshold level ranges.

26. The memory system according to claim 24, wherein the programming circuit further operates with programming voltage conditions that requires a plurality of said successive applications of programming voltage conditions in order to change individual ones of the plurality of addressed cells from one of the threshold level ranges to another adjacent threshold level range.

27. The memory system according to claim 19, wherein the control circuit includes a comparator receiving the monitored threshold level range of the plurality of addressed cells and the input data being programmed into the plurality of addressed cells for verifying when the individual ones of the plurality of cells reach the programmable threshold level that corresponds to the input data being stored therein.

28. The memory system according to claim 19, wherein at least one reference cell is included in individual ones of the blocks of cells, and which additionally comprises means for programming said at least one reference cell to a reference level, and wherein said reading circuit includes means for reading the reference level of the reference cell of the block wherein the plurality of addressed cells exists to verify that any one cell has reached the desired threshold level range.

29. The memory system according to claim 19, wherein the reset circuit includes means operable after application of the reset voltage conditions to an addressed at least one block for adjusting to the reset state any cells of said at least one block that were overerased by the reset voltage condition application.

30. The memory system according to claim 19, wherein the reset circuit includes means for selecting one or more of the blocks for erase, and means responsive to the selection means for simultaneously applying the reset voltage condition to the memory cells within all of the selected blocks.

31. The memory system according to claim 30, wherein the block selecting means includes a register associated with individual ones of the blocks for containing an indication whether the associated block is to be erased.

32. A method of storing multiple bits of binary data in a chunk of non-volatile memory cells which individually have more than two programmable states, comprising:

applying electrical programming parameters in parallel to cells within said chunk,

monitoring the states of individual cells within said chunk, and

terminating application of programming parameters to individual cells within said chunk when they are monitored to have reached desired ones of said more than two programmable states corresponding to the multiple bits of data being stored, while continuing to apply said programming parameters to others of the cells within said chunk, until all of the cells within said chunk are determined to have reached their programmable states corresponding to the multiple bits of data being stored.

33. The method of claim 32, wherein, prior to applying electrical programming parameters to cells within said chunk, at least the cells within said chunk are all reset to a common state different than any of said more than two programmable states.

34. The method of claim 32, wherein, prior to applying electrical programming parameters to the cells wherein said chunk, at least the cells within said chunk are all reset to one of the more than two programmable states.

35. The method of claim 34, wherein resetting at least the cells within said chunk includes initially driving at least all of the cells within said chunk to a common state different than any of said more than two programmable states, and then programming all of at least the cells within said chunk from the common state into one of the more than two programmable states by the following:

applying electrical programming parameters in parallel to at least the cells within said chunk,

monitoring the states in which at least the cells within said chunk are individually programmed, and

terminating application of programming parameters to individual ones of at least the cells within said chunk when they are monitored to have reached said one of the more than two programmable states while continuing to apply said programming parameters to others of the cells within said chunk until all of the cells within said chunk are determined to have reached the said one of the more than two programmable states.

36. An electrically erasable and programmable non-volatile memory system, comprising:

an integrated circuit array of electrically alterable memory cells that are individually programmable into more than two states, thereby individually storing more than one bit of binary data,

a programming circuit that applies appropriate programming parameters in parallel to an addressed plurality of cells,

a reading circuit that verifies in parallel the state into which the addressed plurality of cells are programmed,

means for inhibiting further programming of correctly verified cells among the plurality of addressed cells, and

means for further programming and verifying in parallel the plurality of addressed cells and inhibiting programming of correctly verified cells until all the plurality of addressed cells are verified correctly.

37. A method of operating an EEprom system having memory cells that individually include an electrically floating gate carrying a charge level that is alterable in response to appropriate voltage conditions being applied to the cell in order to set a variable threshold thereof to a desired level that is determinable by reading the cell, said method comprising:

applying said appropriate voltage conditions in parallel to a plurality of said memory cells, thereby to alter the charge levels on the floating gates of said plurality of memory cells to drive their threshold levels to desired levels,

individually monitoring the threshold levels of said plurality of memory cells to set a binary element associated with each such cell, when reaching its desired threshold level, in order to prevent further application of appropriate voltage conditions to said plurality of memory cells from altering the charge level of the associated memory cell, and

continuing the voltage applying and monitoring steps until all of said plurality of cells have reached their desired levels without allowing any individual binary element to be reset as a result of any monitoring its associated memory cell after the binary element is set.

38. The method of claim 37, wherein there are exactly two threshold levels.

39. The method of claim 37, wherein there are more than two threshold levels.