Flash EEprom system with cell by cell programming verification
DCFirst Claim
1. A method of operating an EEprom system having memory cells that individually include an electrically floating gate carrying a charge level that is alterable in response to appropriate voltage conditions being applied to the cell in order to set a variable threshold level thereof into a range that is determinable by reading the cell, said method comprising:
- applying said appropriate voltage conditions in parallel to a plurality of said memory cells, thereby to alter the charge levels on the floating gates of said plurality of memory cells,determining the threshold level ranges in which individual ones of said plurality of memory cells lie, andterminating said application of appropriate voltage conditions to individual ones of said plurality of memory cells upon their being determined to have reached desired threshold level ranges while continuing to apply said appropriate voltage conditions to others of said plurality of cells until all of the plurality of cells are determined to have reached their desired threshold level ranges.
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Abstract
A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement individually verifies the states of a plurality of cells that are being programmed in parallel in order to terminate the programming, as a result of the verification, on a cell-by-cell basis as the cells reach their programmed states.
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Citations
39 Claims
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1. A method of operating an EEprom system having memory cells that individually include an electrically floating gate carrying a charge level that is alterable in response to appropriate voltage conditions being applied to the cell in order to set a variable threshold level thereof into a range that is determinable by reading the cell, said method comprising:
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applying said appropriate voltage conditions in parallel to a plurality of said memory cells, thereby to alter the charge levels on the floating gates of said plurality of memory cells, determining the threshold level ranges in which individual ones of said plurality of memory cells lie, and terminating said application of appropriate voltage conditions to individual ones of said plurality of memory cells upon their being determined to have reached desired threshold level ranges while continuing to apply said appropriate voltage conditions to others of said plurality of cells until all of the plurality of cells are determined to have reached their desired threshold level ranges. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20)
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19. An electrically erasable and programmable read only memory system, comprising:
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an array of electrically alterable memory cells that individually include a field effect transistor having a floating gate and a threshold level that is variable in accordance with an amount of charge carried by the floating gate, said array being divided into blocks of cells that are resettable together, cells within said blocks being addressable for application of programming voltage conditions to individually program them into one of more than two distinct threshold level ranges corresponding to more than one bit of input data per cell, a reset circuit that simultaneously applies reset voltage conditions to the cells within individual blocks to drive the effective threshold levels of such cells to a reset state, a programming circuit that applies the programming voltage conditions to a plurality of addressed cells within a reset block to drive the effective threshold voltage of the addressed cells toward one of the more than two programmable threshold level ranges, a reading circuit that monitors in parallel the threshold level ranges of the plurality of addressed cells, and a control circuit that individually terminates application of the programming voltage conditions to any one of the plurality of addressed cells when the reading circuit verifies that said any one cell has reached the programmable threshold level range that corresponds to the input data being stored therein, while enabling further application of the programming voltage conditions to others of the plurality of addressed cells that have not yet been so verified, until all of the plurality of addressed cells are verified. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. A method of storing multiple bits of binary data in a chunk of non-volatile memory cells which individually have more than two programmable states, comprising:
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applying electrical programming parameters in parallel to cells within said chunk, monitoring the states of individual cells within said chunk, and terminating application of programming parameters to individual cells within said chunk when they are monitored to have reached desired ones of said more than two programmable states corresponding to the multiple bits of data being stored, while continuing to apply said programming parameters to others of the cells within said chunk, until all of the cells within said chunk are determined to have reached their programmable states corresponding to the multiple bits of data being stored. - View Dependent Claims (33, 34, 35)
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36. An electrically erasable and programmable non-volatile memory system, comprising:
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an integrated circuit array of electrically alterable memory cells that are individually programmable into more than two states, thereby individually storing more than one bit of binary data, a programming circuit that applies appropriate programming parameters in parallel to an addressed plurality of cells, a reading circuit that verifies in parallel the state into which the addressed plurality of cells are programmed, means for inhibiting further programming of correctly verified cells among the plurality of addressed cells, and means for further programming and verifying in parallel the plurality of addressed cells and inhibiting programming of correctly verified cells until all the plurality of addressed cells are verified correctly.
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37. A method of operating an EEprom system having memory cells that individually include an electrically floating gate carrying a charge level that is alterable in response to appropriate voltage conditions being applied to the cell in order to set a variable threshold thereof to a desired level that is determinable by reading the cell, said method comprising:
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applying said appropriate voltage conditions in parallel to a plurality of said memory cells, thereby to alter the charge levels on the floating gates of said plurality of memory cells to drive their threshold levels to desired levels, individually monitoring the threshold levels of said plurality of memory cells to set a binary element associated with each such cell, when reaching its desired threshold level, in order to prevent further application of appropriate voltage conditions to said plurality of memory cells from altering the charge level of the associated memory cell, and continuing the voltage applying and monitoring steps until all of said plurality of cells have reached their desired levels without allowing any individual binary element to be reset as a result of any monitoring its associated memory cell after the binary element is set. - View Dependent Claims (38, 39)
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Specification