Secure memory having multiple security levels

• US 5,991,519 A
• Filed: 10/03/1997
• Issued: 11/23/1999
• Est. Priority Date: 10/03/1997
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Terry, Edward L. Jr., Tonge, Phillip D., Baran, Dennis F., Benhammou, Jean-Pierre
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): WRIGHT, NORMAN M
• Application Number:
  US08/943,510
• Time in Patent Office: 781 Days
• Field of Search: 395/186, 395/188.01, 340/825.32, 340/825.31, 340/825.34
• US Class Current: 726/3
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G06Q 20/35765 Access rights to memory zones
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system

Abstract

According to the present invention, a secured memory comprises a first level security zone having an access code controlling access to the secured memory prior to an issuer fuse being blown, a security code attempts counter preventing access to the secured memory when a predetermined number of attempts at matching the access code have been made prior to resetting the security code attempts counter, a plurality of application zones, each of the plurality of application zones comprising: a storage memory zone, an application security zone having an application zone access code controlling access to the storage memory zone after an issuer fuse has been blown, an application zone security code attempts counter preventing access to the application zone when a predetermined number of attempts at matching the application zone access code have been made prior to resetting the application zone security code attempts counter, an erase key partition having an erase key code controlling erase access to the storage memory zone after an issuer fuse has been blown, and an erase key attempts counter preventing erase access to the application zone when a predetermined number of attempts at matching the erase key code have been made prior to resetting the erase key attempts counter.

Claims

1. A secured memory comprising:

a first level security zone having an access code controlling access to said secured memory prior to an issuer fuse being blown;

a security code attempts counter preventing access to said secured memory when a predetermined number of attempts at matching said access code have been made prior to resetting said security code attempts counter;

a plurality of application zones, each of said plurality of application zones comprising;

a storage memory zone;

an application security zone having an application zone access code controlling access to said storage memory zone after an issuer fuse has been blown;

an application zone security code attempts counter preventing access to said application zone when a predetermined number of attempts at matching said application zone access code have been made prior to resetting said application zone security code attempts counter;

an erase key partition having an erase key code controlling erase access to said storage memory zone after an issuer fuse has been blown; and

an erase key attempts counter preventing erase access to said application zone when a predetermined number of attempts at matching said erase key code have been made prior to resetting said erase key attempts counter.