Method and system of checking for open circuit connections within an integrated-circuit design represented by a hierarchical data structure

• US 5,991,521 A
• Filed: 03/31/1997
• Issued: 11/23/1999
• Est. Priority Date: 03/31/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Quay, Stephen Thomas, Gabele, Carol Ivash, Smith, Clay Chip
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/829,578
• Time in Patent Office: 967 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 395/500, 395/500.05, 395/500.06, 324/512, 702/58, 702/59
• US Class Current: 716/112
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

An integrated-circuit design is provided which is represented by a hierarchial data structure. In accordance with the method and system of the present invention, an integrated-circuit design which includes at least one parent circuit represented by a set of parent circuit level data and at least one child circuit represented by a set of child circuit level data. For an open circuit connection within the child circuit, a determination is made as to whether or not the open circuit connection is permissible. In response to a determination that the open circuit connection is permissible, another determination is made as to whether or not the number of I/O pins within the child circuit is greater than the number of open circuit connections within the child circuit. In response to a determination that the number of I/O pins within the child circuit is greater than the number of open circuit connections within the child circuit, the set of child circuit level data is integrated into the set of parent circuit level data. Finally, a determination is made as to whether or not the open circuit connection is closed within the integrated set of parent circuit level data. An error message will be displayed if the open circuit connection is not closed within the integrated set of parent circuit level data.

Claims

1. A method of checking for open circuit connections within an integrated circuit design, said method comprising the steps of:

for an integrated circuit design having at least one parent circuit represented by a set of parent circuit level data and at least one child circuit represented by a set of child circuit level data, wherein said at least one parent circuit is at a higher hierarchial level than said at least one child circuit, determining whether or not a number of I/O pins within said at least one child circuit is greater than a number of open circuit connections specified for said at least one child circuit by a user;

presenting an error message in response to a determination that said number of I/O pins within said at least one child circuit is not greater than said number of open circuit connections specified for said at least one child circuit by said user.

2. The method according to claim 1, wherein said method further includes a step of integrating said set of child circuit level data into said set of parent circuit level data, in response to a determination that said number of I/O pins within said at least one child circuit is greater than said number of open circuit connections specified for said at least one child circuit by said user.

3. The method according to claim to 2, wherein said method further includes a step of determining whether or not said open circuit connection is closed within said integrated set of parent circuit level data.

4. the method according to claim 3, wherein said method further includes a step of presenting an error message in response to a determination that said open circuit connection is not closed within said set of integrated parent circuit level data.

5. A computer system capable of checking for open circuit connections within an integrated circuit design, said computer system comprising:

for an integrated circuit design having at least one parent circuit represented by a set of parent circuit level data and at least one child circuit represented by a set of child circuit level data, wherein said at least one parent circuit is at a higher hierarchial level than said at least one child circuit, means for determining whether or not a number of I/O pins within said at least one child circuit is greater than a number of open circuit connections specified for said at least one child circuit by a user; and

means for presenting an error message in response to a determination that said number of I/O pins within said at least one child circuit is not greater than said number of open circuit connections specified for said at least one child circuit by said user is not closed within said parent circuit.

6. The computer system according to claim 5, wherein said computer system further includes a means for integrating said set of child circuit level data into said set of parent circuit level data, in response to a determination that said number of I/O pins within said at least one child circuit is greater than said number of open circuit connections specified for said at least one child circuit by said user.

7. The computer system according to claim 6, wherein said computer system further includes a means for determining whether or not said open circuit connection is closed within said integrated set of parent circuit level data.

8. The computer system according to claim 7, wherein said computer system further includes a means for presenting an error message in response to a determination that said open circuit connection is not closed within said set of integrated parent circuit level data.

9. A computer program product residing on a computer usable medium for checking for open circuit connections within an integrated circuit design, wherein said integrated circuit design is represented by at least one parent circuit level and at least one child circuit level, wherein said at least one parent circuit is at a higher hierarchial level than said at least one child circuit, said computer program product comprising:

program code means for determining whether or not a number of I/O pins within said at least one child circuit is greater than a number of open circuit connections specified for said at least one child circuit by a user; and

program code means for presenting an error message in response to a determination that said number of I/O pins within said at least one child circuit is not greater than said number of open circuit connections specified for said at least one child circuit by said user is not closed within said parent circuit.

10. The computer program product according to claim 9, wherein said computer program product further includes a program code means for integrating said set of child circuit level data into said set of parent circuit level data, in response to a determination that said number of I/O pins within said at least one child circuit is greater than said number of open circuit connections specified for said at least one child circuit by said user.

11. The computer program product according to claim 10, wherein said computer program product further includes a means for determining whether or not said open circuit connection is closed within said integrated set of parent circuit level data.

12. The computer program product according to claim 11, wherein said computer program product further includes a program code means for presenting an error message in response to a determination that said open circuit connection is not closed within said set of integrated parent circuit level data.