Testing of hardware by using a hardware system environment that mimics a virtual system environment

• US 5,991,529 A
• Filed: 05/16/1997
• Issued: 11/23/1999
• Est. Priority Date: 05/16/1997
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Chue, Harry M., Cox, Steven R.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Broda, Samuel
• Application Number:
  US08/857,154
• Time in Patent Office: 921 Days
• Field of Search: 395/500, 364/578
• US Class Current: 703/9
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A technique for testing a hardware implementation of an integrated circuit design using test algorithms developed for testing a software model of the integrated circuit design. A software model is created for a design of the integrated circuit. The software model is a software algorithm that emulates behavior of the integrated circuit. In addition, a virtual environment for the software model is also constructed. The virtual environment is a software algorithm that emulates an actual environment anticipated for the integrated circuit. Diagnostic tests are performed on the software model while it is operating in the virtual environment. These tests are used to verify and analyze the design for the integrated circuit. Based upon the results of the diagnostic tests, the design is modified as necessary. Once the design for the integrated circuit has been verified by testing the software model, an actual hardware circuit is constructed that implements the software model. In addition, an actual hardware environment is constructed that implements the virtual environment. Accordingly, the software model and the virtual environment are transformed into equivalent hardware circuits. Because of the equivalency between the software model and the hardware circuit and between the virtual environment with the hardware environment, the same diagnostic tests that were used to verify and analyze the software model in the virtual environment can be used to verify and analyze the hardware circuit in the hardware environment. This results in good test coverage for the integrated circuit design and reduced expense for developing the diagnostic tests.

Claims

1. An apparatus for verifying a design for a hardware circuit, the apparatus comprising:

a. a virtual system, wherein the virtual system comprises a host computer system programmed according to a first software program for causing the host computer to emulate the design for the hardware circuit;

b. a first test program for stimulating the virtual system to execute a function wherein the first test program comprises a first set up file and a first diagnostic test;

c. a hardware system, wherein the hardware system is functionally equivalent to the virtual system and wherein a parameter of the hardware system is selectively configured according to a parameter contained in the first set up file; and

d. a second test program for stimulating the hardware system to execute a function wherein the second test program comprises a second set up file and second diagnostic test and wherein the second diagnostic test is identical to the first diagnostic test.

2. The apparatus according to claim 1 wherein the virtual system is logically divisible into a software model of the design and into a virtual environment for the software model.

3. The apparatus according to claim 2 wherein the hardware system is physically divisible into a hardware circuit having equivalent functionality to the software model and into a hardware environment having equivalent functionality to the virtual environment.

4. The apparatus according to claim 1 wherein the parameter of the hardware system is selected from the group consisting of:

assigning a memory segment for a particular function, selecting a number of wait states used for accessing a memory segment, controlling a system clock frequency, enabling a parity checking function, enabling a DMA function, enabling a DMA request, enabling a random external interrupt, controlling a cache burst refill size, selecting a cache burst word to be retried, and controlling a power supply voltage.

5. An apparatus for verifying a design for a hardware circuit, the apparatus comprising:

a. a software model for the design, wherein the software model is a first software program for causing a host computer to emulate the design;

b. a virtual environment wherein the virtual environment is a second software program for causing the host computer to emulate an environment for the design;

c. a first test program for stimulating the software model to execute a function within the virtual environment wherein the first test program comprises a first set up file and a first diagnostic test;

d. a hardware circuit for the design, wherein the hardware circuit is functionally equivalent to the software model;

e. a hardware environment operatively coupled to the hardware circuit, wherein the hardware environment is functionally equivalent to the virtual environment; and

f. a second test program for stimulating the hardware model to execute a function within the hardware environment wherein the second test program comprises a second set up file and second diagnostic test and wherein the second diagnostic test is identical to the first diagnostic test.

6. The apparatus according to claim 5 wherein the first set up file differs from the second set up file according to differences between initialization requirements of the virtual environment and initialization requirements of the hardware environment.

7. The apparatus according to claim 5 wherein the hardware environment is selectively configured according to a parameter contained in the first set up file.

8. A method of verifying a design for a hardware circuit, the method comprising steps of:

a. constructing a software model, wherein the software model is a first software algorithm which emulates the design for the hardware circuit;

b. constructing a virtual environment for interacting with the software model, wherein the virtual environment is a second software algorithm which emulates an environment for the design for the hardware circuit;

c. testing the software model by performing a diagnostic test on the software model;

d. constructing a hardware circuit which is functionally equivalent to the software model;

e. constructing a hardware environment operatively coupled to the hardware circuit wherein the hardware environment is functionally equivalent to the virtual environment; and

f. testing the hardware circuit by performing the diagnostic test on the hardware circuit.

9. The method according to claim 8 further comprising a step of integrating the hardware circuit into a single chip.

10. The method according to claim 8 further comprising steps of:

a. initializing the software model according to a first set up file before testing the software model; and

b. initializing the hardware circuit according to a second set up file before testing the hardware circuit.

11. The method according to claim 10 further comprising a step of configuring the hardware environment according to a predetermined parameters before testing the hardware circuit.