Memory transactions on a low pin count bus

• US 5,991,841 A
• Filed: 09/24/1997
• Issued: 11/23/1999
• Est. Priority Date: 09/24/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bennett, Joseph A., Poisner, David I., Gafken, Andrew H.
• Primary Examiner(s): Auve, Glenn A.
• Application Number:
  US08/936,848
• Time in Patent Office: 790 Days
• Field of Search: 395/828, 395/830, 395/833, 395/284, 395/651, 395/652, 395/879, 710/8, 710/10, 710/13, 710/59, 710/104, 713/1, 713/2
• US Class Current: 710/104
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.

Claims

1. A system comprising:

a bus comprising a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information;

a memory device coupled to the bus and storing system start-up information; and

a host coupled to the bus and writing first control information to the memory device via the bus to indicate a memory transaction in which a part of the system start-up information is communicated between the host and the memory device;

wherein the memory device provides second control information to the host via the bus to synchronize operation of the memory device with the host.

2. The system of claim 1, wherein the bus further comprises an independent control signal line for carrying a control signal that indicates a beginning of the memory transaction.

3. The system of claim 2, wherein the control signal on the independent control signal line indicates aborting the memory transaction.

4. The system of claim 1, wherein the bus includes an independent clock signal line for carrying a clock signal, and wherein the memory device synchronously communicates the system start-up information with the host with respect to the clock signal.

5. The system of claim 1, wherein the host writes third control information to the memory device via the bus to indicate a memory address in the memory device.

6. The system of claim 5, wherein the host writes fourth control information to the memory device via the bus to indicate a number of bytes to be transferred in the memory transaction.

7. The system of claim 1, wherein the memory device provides the second control information to the bus until data is ready to be output to the bus by the memory device.

8. The system of claim 1, wherein the second control information comprises an indication of an error in the memory transaction.

9. The system of claim 1, wherein the host comprises a processor.

10. The system of claim 1, wherein the host comprises a chip set.

11. The system of claim 1, wherein the plurality of general purpose signal lines comprises four general purpose signal lines.

12. The system of claim 1, wherein the system comprises a communication system.

13. A system comprising:

a bus comprising a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information;

a memory device coupled to the bus and storing system start-up information; and

a host coupled to the bus and writing first control information to the memory device via the bus to indicate a memory transaction in which a part of the system start-up information is communicated between the host and the memory device, wherein the host writes second control information to the memory device via the bus to indicate a memory address in the memory device, and wherein the host writes third control information to the memory device via the bus to indicate a number of bytes to be tranferred in the memory transaction, and wherein the host writes fourth control information to the memory device via the bus to turn control of the bus over to the memory device.

14. A system comprising:

a memory device storing system start-up information;

a bus comprising a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information, wherein the bus further comprises an independent control signal line for carrying a control signal that indicates a low power mode for the memory device; and

a host coupled to the bus and writing first control information to the memory device via the bus to indicate a memory transaction in which a part of the system start-up information is communicated between the host and the memory device.

15. A method of performing a memory transaction between a host and a memory device across a bus comprising a plurality of general purpose signal lines and a separate control line, wherein the memory device stores system start-up information, the method comprising the steps of:

asserting a control signal on the control line to indicate the start of the memory transaction;

writing first control information from the host to the memory device on the plurality of general purpose signal lines to indicate that the memory transaction comprises the host writing a unit of data to the memory device;

writing second control information from the host to the memory device on the plurality of general purpose signal lines to indicate an address in the memory device to which the unit of data will be written;

writing third control information from the host to the memory device on the plurality of general purpose signal lines to indicate a number of bytes in the unit of data to be transferred;

writing the unit of data to the memory device via the general purpose signal lines;

turning control of the bus over to the memory device;

providing fourth control information from the memory device to the bus to indicate a length of time before the memory device will turn control of the bus over to the host; and

turning control of the bus over to the host.

16. The method of claim 15, further comprising the steps of:

writing device selection control information from the host to the plurality of general purpose signal lines; and

the memory device writing the unit of data to a memory location in the memory device if the device selection control information matches an identification of the memory device.

17. A method of performing a memory transaction between a host and a memory device across a bus comprising a plurality of general purpose signal lines and a separate control line, wherein the memory device stores system start-up information, the method comprising the steps of:

asserting a control signal on the control line to indicate the start of the memory transaction;

writing first control information from the host to the memory device on the plurality of general purpose signal lines to indicate that the memory transaction comprises the host writing a unit of data to the memory device;

writing second control information from the host to the memory device on the plurality of general purpose signal lines to indicate an address in the memory device to which the unit of data will be written;

writing third control information from the host to the memory device on the plurality of general purpose signal lines to indicate a number of bytes in the unit of data to be transferred;

writing the unit of data to the memory device via the general purpose signal lines; and

writing fourth control information from the memory device to the host on the plurality of general purpose signal lines to indicate an error in the memory transaction.

18. The method of claim 17, further comprising the steps of:

writing device selection control information from the host to the plurality of general purpose signal lines; and

the memory device writing the unit of data to a memory location in the memory device if the device selection control information matches an identification of the memory device.

19. A method of performing a memory transaction between a host and a memory device across a bus comprising a plurality of general purpose signal lines that carry time-multiplexed address, data, and control signals and a separate control line, wherein the memory device stores system start-up information, the method comprising the steps of:

asserting a control signal on the control line to indicate the start of the memory transaction;

writing first control information from the host to the memory device on the plurality of general purpose signal lines to indicate that the memory transaction comprises the host reading a unit of data from the memory device;

writing second control information from the host to the memory device on the plurality of general purpose signal lines to indicate an address in the memory device from which the unit of data will be read;

writing third control information from the host to the memory device on the plurality of general purpose signal lines to indicate a number of bytes in the unit of data to be read;

turning control of the bus over to the memory device;

writing fourth control information from the memory device to the host on the plurality of general purpose signal lines until the unit of data is ready to be read from the memory device; and

reading the unit of data from the memory device via the general purpose signal lines.

20. The method of claim 19, wherein the fourth control information comprises an indication of an error in the memory transaction.

21. The method of claim 19, further comprising the steps of:

writing device selection control information from the host to the plurality of general purpose signal lines; and

reading the unit of data from the memory device if the device selection control information matches an identification of the memory device.

22. A system comprising:

a bus having a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information;

a peripheral device coupled to the bus; and

a host coupled to the bus, wherein the peripheral device communicates wait state information over the bus to the host device.

23. The system of claim 22, wherein the peripheral device communicates an error message over the bus to the host.