Redundant bus bridge systems and methods using selectively synchronized clock signals

• US 5,991,844 A
• Filed: 04/17/1998
• Issued: 11/23/1999
• Est. Priority Date: 04/17/1998
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Khosrowpour, Farzad
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US09/062,282
• Time in Patent Office: 585 Days
• Field of Search: 710/128, 710/129, 710/126, 710/101, 710/100, 710/131, 710/33, 710/60, 710/106, 709/232, 713/501, 713/503, 713/400, 714/1, 714/4, 395/559, 370/402, 370/285, 370/466, 375/219, 327/141
• US Class Current: 710/312
• CPC Class Codes: G06F 11/2005 using redundant communication controllers
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: G06F 13/405 where the bridge performs a synchronising function

Abstract

A redundant bus bridge system for communicating between a first bus and a second bus includes a first clock generator operative to produce a first clock signal and a second clock generator operative to produce a second clock signal. A first bus bridge, e.g., a first RAID controller, connects the first bus and the second bus and is responsive to the first clock generator and the second clock generator. The first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with a selected one of the first clock signal and the second clock signal. A second bus bridge, e.g., a second RAID controller, connects the first bus and the second bus and is responsive to the first clock generator and the second clock generator. The second bus bridge is operative to transfer data between the first bus and the second bus in synchronism with a selected one of the first clock signal and the second clock signal. According to aspects of the present invention, the first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with the second clock signal when the second bus bridge is operational, and the first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with the first clock signal when the second bus bridge is non-operational.

Claims

1. A redundant bus bridge system for communicating between a first bus and a second bus, the system comprising:

a first clock generator operative to produce a first clock signal;

a second clock generator operative to produce a second clock signal;

a first bus bridge connecting the first bus and the second bus and responsive to said first clock generator and said second clock generator, wherein said first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with a selected one of said first clock signal and said second clock signal; and

a second bus bridge connecting the first bus and the second bus and responsive to said first clock generator and said second clock generator, wherein said second bus bridge is operative to transfer data between the first bus and the second bus in synchronism with a selected one of said first clock signal and said second clock signal.

2. A system according to claim 1, wherein said first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with said second clock signal when said second bus bridge is operational, and wherein said first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with said first clock signal when said second bus bridge is non-operational.

3. A system according to claim 1, further comprising:

a first selective clock synchronizing circuit configured to receive said first clock signal and said second clock signal and operative to produce a first synchronized clock signal synchronized to one of said first clock signal and said second clock signal; and

a second selective clock synchronizing circuit configured to receive said first clock signal and said second clock signal and operative to produce a second synchronized clock signal synchronized to one of said first clock signal and said second clock signal; and

wherein said first bus bridge is configured to receive said first synchronized clock signal and operative to transfer data between the first bus and the second bus responsive thereto; and

wherein said second bus bridge is configured to receive said second synchronized clock signal and operative to transfer data between the first bus and the second bus responsive thereto.

4. A system according to claim 3, wherein said first selective clock synchronizing circuit is operative to synchronize said first synchronized clock signal to said second clock signal when said second bus bridge is operational, and wherein said first selective clock synchronizing means is operative to synchronize said first synchronized clock signal to said first clock signal when said second bus bridge is non-operational.

5. A system according to claim 3, wherein said first selective clock synchronizing circuit is operative to synchronize said first synchronized clock signal to said second clock signal when said second clock signal is valid and to synchronize said first synchronized clock signal to said first clock signal when said second clock signal is invalid.

6. A system according to claim 3, wherein said first selective clock synchronizing circuit comprises:

a phase-locked loop configured to receive an applied clock signal and operative to synchronize said first synchronized clock signal thereto; and

a switch configured to receive said first clock signal and said second clock signal and operative to selectively apply one of said first clock signal and said second clock signal to said phase-locked loop.

7. A system according to claim 6:

wherein said first selective clock synchronizing circuit further comprises a clock status monitoring circuit operative to determine a status of said second clock signal and to produce a command signal in based on the determined status of said second clock signal; and

wherein said switch is responsive to said command signal to apply one of said first clock signal and said second clock signal to said phase-locked loop.

8. A system according to claim 7, wherein said first clock signal has a first frequency, wherein said first synchronized clock signal has a second frequency, and wherein said clock status monitoring circuit comprises a clock comparing circuit operative to compare said first frequency and said second frequency to determine a status of said second clock signal.

9. A system according to claim 3, comprising:

a first circuit assembly including said first bus bridge, said first clock generator and said first selective clock synchronizing circuit; and

a second circuit assembly including said second bus bridge, said second clock generator and said second selective clock synchronizing circuit; and

a conductor assembly connecting said first circuit assembly and said second circuit assembly such that said first clock signal is conveyed from said first circuit assembly to said second circuit assembly and said second clock signal is conveyed from said second circuit assembly to said first circuit assembly.

10. A system according to claim 9, wherein said conductor assembly comprises a backplane and wherein said first and second circuit assemblies are releasably connectable to said backplane.

11. A system according to claim 3 further comprising a data bus connecting said first bus bridge and said second bus bridge, and wherein said first bus bridge and said second bus bridge are operative to transfer data therebetween over said data bus in synchronism with a selected one of said first clock signal and said second clock signal.

12. A system according to claim 11:

wherein said first bus bridge comprises a first cache responsive to said first synchronized clock signal and operative to cache data transfers between the first bus and the second bus;

wherein said second bus bridge comprises a second cache responsive to said second synchronized clock signal and operative to cache data transfers between the first bus and the second bus; and

wherein said data bus connects said first and second caches.

13. A system according to claim 12, further comprising:

a first transceiver connecting said first cache and said data bus and operative to communicate between said first cache and said data bus responsive to said first synchronized clock signal; and

a second transceiver connecting said second cache and said data bus and operative to communicate between said second cache and said data bus responsive to said second synchronized clock signal.

14. A system according to claim 3, wherein said first bus bridge and said second bus bridge comprise respective first and second RAID controllers.

15. A circuit assembly for a redundant bus bridge system that communicates between a first bus and a second bus, the circuit assembly comprising:

a clock generator operative to produce a local clock signal;

a selective clock synchronizing circuit configured to receive said local clock signal and an externally-supplied remote clock signal and operative to produce a synchronized clock signal synchronized to a selected one of said local clock signal and said remote clock signal; and

a bus bridge connected to said selective clock synchronizing circuit and operative to transfer data between the first bus and the second bus responsive to said synchronized clock signal.

16. An assembly according to claim 15, wherein said selective clock synchronizing circuit is operative to synchronize said synchronized clock signal to said remote clock signal when said remote clock signal is valid and to synchronize said synchronized clock signal to said local clock signal when said remote clock signal is invalid.

17. An assembly according to claim 15, wherein said selective clock synchronizing circuit comprises:

a phase-locked loop configured to receive an applied clock signal and operative to synchronize said synchronized clock signal thereto; and

a switch configured to receive said local clock signal and said remote clock signal and operative to selectively apply one of said local clock signal and said remote clock signal to said phase-locked loop.

18. An assembly according to claim 17:

wherein said selective clock synchronizing circuit further comprises a clock status monitoring circuit operative to determine a status of said remote clock signal and operative to produce a command signal based on the determined status of said remote clock signal; and

wherein said switch is responsive to said command signal to apply one of said local clock signal and said remote clock signal to said phase-locked loop.

19. An assembly according to claim 18, wherein said local clock signal has a first frequency, wherein said synchronized clock signal has a second frequency, and wherein said clock status monitoring circuit comprises a clock comparing circuit operative to compare said first frequency and said second frequency to determine a status of said remote clock signal.

20. An assembly according to claim 15, wherein said bus bridge comprises a RAID controller.

21. In a redundant bus bridge system including a first and second bus bridges included in respective first and second circuit assemblies, a method of operating comprising the steps of:

generating a first clock signal on the first circuit assembly;

generating a second clock signal on the second circuit assembly; and

transferring data over the first bus bridge and the second bus bridge in synchronism with a selected one of the first clock signal and the second clock signal.

22. A method according to claim 21, comprising the steps of:

transferring data over the first bus bridge in synchronism with the second clock signal when the second bus bridge is operational; and

transferring data over the first bus bridge in synchronism with the first clock signal when the second bus bridge is non-operational.

23. A method according to claim 21, further comprising the steps of:

producing a first synchronized clock signal synchronized to one of the first clock signal and the second clock signal;

producing a second synchronized clock signal synchronized to one of the first clock signal and the second clock signal;

transferring data over the first bus bridge responsive to the first synchronized clock signal; and

transferring data over the second bus bridge responsive to the second synchronized clock signal.

24. A method according to claim 23, comprising the steps of:

synchronizing the first synchronized clock signal to the second clock signal when the second bus bridge is operational; and

synchronizing the first synchronized clock signal to the first clock signal when the second bus bridge is non-operational.

25. A method according to claim 23, comprising the steps of:

synchronizing the first synchronized clock signal to the second clock signal when the second clock signal is valid; and

synchronizing the first synchronized clock signal to the first clock signal when said second clock signal is invalid.

26. A method according to claim 21, comprising the steps of:

determining a status of the second clock signal; and

synchronizing the first synchronized clock signal to one of the first clock signal and the second clock signal based on the determined status of the second clock signal.

27. A method according to claim 26, wherein the first clock signal has a first frequency, wherein the first synchronized clock signal has a second frequency, and wherein said step of determining comprises the step of comparing the first frequency and the second frequency to determine a status of the second clock signal.