Memory apparatus and data processor using the same

• US 5,991,902 A
• Filed: 03/06/1997
• Issued: 11/23/1999
• Est. Priority Date: 08/07/1991
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yoshida, Toyohiko
• Primary Examiner(s): Tu, Trinh L.
• Application Number:
  US08/812,464
• Time in Patent Office: 992 Days
• Field of Search: 371/21.1, 371/21.2, 371/40.1, 371/10.2, 371/10.3, 371/21.6, 364/247.3, 364/245.5, 364/245.9, 364/365.3, 364/243.41, 364/964.2, 364/243.4, 364/243.7, 364/245.3, 364/246.3, 364/268.3, 364/268.5 , 364/943.91, 364/944, 364/944.2, 364/944.3, 364/966.4, 364/970.1, 395/182.13, 395/182.19, 395/183.01, 395/183.05, 395/183.18, 395/184.01, 395/185.02, 395/185.07, 395/185.06, 395/182.03, 711/3, 711/111, 711/112, 711/113, 711/129, 711/133, 711/134, 711/144, 711/158
• US Class Current: 714/710
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring

Abstract

A memory apparatus and a data processor using the same comprises, a memory mechanism, having a signal input terminal into which a predetermined signal is inputted, a memory unit consisting of first, second and third memories, a fourth memory and a control unit which replaces the first or second memory with the third memory by switching electrical connections between the memories of the memory unit according to information written into the fourth memory, and furthermore, an operation unit which diagnoses failures in the memory mechanism in case the predetermined signal is inputted from the signal input terminal, in case the failure is diagnosed in the first memory allows the control unit to replace the first memory with the third memory by writing a first value into the fourth memory, and in case the failure is diagnosed in the second memory allows the control unit to replace the second memory with the third memory by writing a second value into the fourth memory. Since the failure in the memory array unit can be relieved, manufacturing yields of the memory apparatus and the data processor including the same are improved.

Claims

1. A memory apparatus, comprising:

a) a buffer memory mechanism, having;

a memory unit comprising a plurality of entries and a spare entry, each entry including a valid bit, a tag field and a data field, said valid bits, tag fields and data fields each having a value,

a control memory connected to said memory unit, wherein said control memory stores values of access enabling bits corresponding to each of said entries of said memory unit, and

a hit or miss judging unit which determines whether said data field value of one of said entries is valid or invalid according to said associated valid bit and tag field values when said corresponding access enabling bit is a first value, and determines that one of said entries is invalid irrespective of said data field value when said corresponding access enabling bit is a second value;

b) an operation mechanism connected to said buffer memory mechanism, having a register and an operation circuit, said operation mechanism capable of writing data into and reading data from said buffer memory mechanism for operation between the data; and

c) a diagnosis circuit, said diagnosis circuit including;

means for diagnosing failures in said entries of said memory unit,

means for setting said access enabling bits corresponding to the entries in which no failure is diagnosed to said first value, and for setting said access enabling bits corresponding to the entries in which a failure is diagnosed to said second value, so as to invalidate said entries in which a failure is diagnosed; and

means for replacing one of said entries in which a failure is diagnosed with said spare entry.

2. A data processor, comprising:

a) a buffer memory mechanism, having;

a memory unit comprising a plurality of entries and a spare entry each entry, including a valid bit, a tag field and a data field, and

a control memory connected to said memory unit, wherein said control memory stores values of access enabling bits corresponding to each of said entries of said memory unit, and

b) an operation mechanism connected to said buffer memory mechanism, having a register and an operation circuit, said operation mechanism capable of writing data into and reading data from said buffer memory mechanism for operation between the data;

wherein said operation mechanism includes;

means for diagnosing failures in the entries of said memory unit,

means for invalidating said entries in which a failure is diagnosed, by setting said access enabling bits corresponding to said entries in which no failure is diagnosed to a first value, and by setting said access enabling bits corresponding to said entries in which a failure is diagnosed to a second value; and

means for replacing one of said entries in which a failure is diagnosed with said spare entry.

3. A method of relieving failures in a memory unit having a plurality of entries and a spare entry, each entry including a valid bit, a tag field and a data field, said memory unit coupled to a control memory, wherein said control memory stores values of access enabling bits corresponding to each of said entries of said memory unit, the method comprising the steps of:

diagnosing failures in the entries of said memory unit;

invalidating entries in which a failure is diagnosed; and

replacing one of said entries in which a failure is diagnosed with said spare entry.

4. The method of claim 3, wherein said step of invalidating entries in which a failure is diagnosed includes the steps of:

setting said access enabling bits corresponding to said entries in which no failure is diagnosed to a first value; and

setting said access enabling bits corresponding to said entries in which a failure is diagnosed to a second value.