Process and device for testing a memory element

• US 5,991,905 A
• Filed: 08/22/1997
• Issued: 11/23/1999
• Est. Priority Date: 08/24/1996
• Status: Expired due to Fees

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Trojacher, Peter, Gagea, Leonard
• Primary Examiner(s): Chung, Phung M.
• Application Number:
  US08/919,067
• Time in Patent Office: 823 Days
• Field of Search: 714/721, 714/718, 714/799
• US Class Current: 714/721
• CPC Class Codes: F02D 41/249 Methods for preventing the loss of data
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G06F 11/0754 by exceeding limits
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

A device and a process for testing a memory element are described. A second memory element is connected in parallel to the first memory element. In order to measure the charge status of the first memory element, the second memory element is brought into a predefined first status and the time required by the second memory element to go from the first status to a second status is measured. This time is analyzed in order to test the memory element.

Claims

1. A method for testing a charge status of a first memory element, the first memory element being connected in parallel to a second memory element, the method comprising the steps of:

charging the second memory element into a predefined first status;

measuring a time period for the second memory element to discharge from the predefined first status to a predefined second status; and

analyzing the measured time period to test the charge status of the first memory element.

2. The method according to claim 1, wherein the measuring step includes measuring the time period multiple times, the charge status of the first memory element changing between each of the multiple measuring time periods.

3. The method according to claim 2, wherein the charge status of the first memory element and a charge status of the second memory element are indicated as a function of the measured time periods.

4. The method according to claim 2, wherein each of the measured time periods is compared with at least one of another measured time period and a predefined value.

5. The method according to claim 2, further comprising the step of calculating a data value of the first memory element as a function of the measured time periods.

6. A device for testing a first memory element, comprising:

a second memory element connected in parallel to the first memory element;

a charge circuit charging the second memory element to a predefined first charged status to measure a charge status of the first memory element; and

means for measuring a time period required by the second memory element to transition from the predefined first charged status to a first discharged status, the measured time period being analyzed to test the first memory element.

7. The device according to claim 6, wherein the first and second memory elements include capacitors.

8. The device according to claim 6, wherein the first memory element indicates a status of a controller.

9. A method for testing a first memory element, the first memory element being connected to a second memory element, the method comprising the steps of:

charging the second memory element to a predefined charged status;

measuring a time period for the second memory element to switch from the predefined charged status to a predefined discharged status; and

analyzing the measured time period to test the first memory element.

10. A device for testing a first memory element, comprising:

a second memory element coupled to the first memory element;

a first switch coupling a supply voltage to the first memory element;

a second switch coupled to the second memory element; and

a control device connected to the second switch, the control device including a monitor measuring a time for the second element to transition between a first charged status and a first discharged status, the control device analyzing the measured time to test the first memory element.