Parallel decompressor and related methods and apparatuses

• US 5,991,909 A
• Filed: 10/15/1996
• Issued: 11/23/1999
• Est. Priority Date: 10/15/1996
• Status: Expired due to Term

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Tyszer, Jerzy, Rajski, Janusz
• Primary Examiner(s): Tu, Trinh L.
• Application Number:
  US08/730,066
• Time in Patent Office: 1,134 Days
• Field of Search: 371/22.34, 371/22.31, 371/22.32, 371/22.33, 371/22.4, 371/22.5, 371/22.6, 371/27.1, 371/27.2, 371/27.4, 371/27.7, 395/183.06, 395/183.08, 364/717, 364/715.02, 324/73.1, 714/729, 714/726, 714/727, 714/728, 714/735, 714/733, 714/734, 714/738, 714/739, 714/741, 714/744, 714/30, 714/32
• US Class Current: 714/729
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern

Abstract

A parallel decompressor capable of concurrently generating in parallel multiple portions of a deterministic partially specified data vector is disclosed. The parallel decompressor is also capable of functioning as a PRPG for generating pseudo-random data vectors. The parallel decompressor is suitable for incorporation into BIST circuitry of ICs. For BIST circuitry with multiple scan chains, the parallel decompressor may be incorporated without requiring additional flip-flops (beyond those presence in the LFSR and scan chains). In one embodiment, an incorporating IC includes boundary scan design compatible with the IEEE 1194.1 standard. Multiple ones of such ICs may be incorporated in a circuit board. Software tools for generating ICs with boundary scan having BIST circuitry incorporated with the parallel decompressor, and for computing the test data seeds for the deterministic partially specified test vectors are also disclosed.

Claims

1. An apparatus comprising a parallel data generator to dynamically generate in parallel a plurality of portions of a deterministic data vector, the parallel data generator being formed with a linear feedback shift register (LFSR) and multiple pluralities of serially coupled flip-flops, wherein the LFSR and the multiple pluralities of serially coupled flip-flops are structurally coupled to allow the LFSR to concurrently output in parallel different data bits to different ones of the multiple pluralities of serially coupled flip-flops, and the multiple pluralities of serially coupled flip-flops to concurrently feed back in parallel different data bits to different parts of the LFSR.

2. The apparatus as set forth in claim 1, wherein the parallel data generator further includes a plurality of unate gates for disabling the concurrent feedback of data bits from the multiple pluralities of serially coupled flip-flops to the LFSR, allowing the LFSR to function as a pseudo-random pattern generator for generating pseudo-random data vectors.

3. The apparatus as set forth in claim 1, wherein the apparatus further comprises a plurality of parallel scan chains, and the multiple pluralities of serially coupled flip-flops are member flip-flops of the parallel scan chains.

4. The apparatus as set forth in claim 1, wherein the parallel data generator is further formed with a plurality of linear logical elements for modifying the different data bits being concurrently output and provided to different ones of the multiple pluralities of serially coupled flip-flops by the LFSR, except for one of the multiple pluralities of serially coupled flip-flops.

5. The apparatus as set forth in claim 1, wherein the parallel generator is further formed with a plurality of data paths for serially coupling the multiple pluralities of serially coupled flip-flops to form a shift register, in conjunction with the LFSR, to facilitate loading of a data seed.

6. The apparatus as set forth in claim 5, wherein the parallel data generator is further formed with a plurality of multiplexors for selecting for the multiple pluralities of serially coupled flip-flop either the corresponding different data bits being provided by the LFSR or data bits being provided by the predecessor series of the serially coupled flip-flops.

7. The apparatus as set forth in claim 5, wherein the parallel data generator is further formed with a plurality of unate gates to modify the different data bits being output and provided by the LFSR, and to modify the data bits being provided by predecessor series of the serially coupled flip-flops.

8. The apparatus as set forth in claim 1, wherein the parallel data generator is further formed with a multiplexor for selecting for the LFSR either a data seed or a feedback data bit from the LFSR itself.

12. The integrated circuit as set forth in claim 1, wherein the integrated circuit further includes boundary scan registers.

9. An apparatus comprising a dual mode pseudo-random pattern generator (PRPG)/parallel decompressor to generate pseudo-random data vectors using a single LFSR while operating in a first mode, and to generate deterministic partially specified data vectors while operating in a second mode, with multiple portions of each deterministic partially specified data vector being generated in parallel using the same single LFSR.

10. The apparatus as set forth in claim 9, wherein the dual purpose PRPG/parallel decompressor further includes a plurality of unate gates to enable a plurality of feedback data bits to be provided to the LFSR while operating in the second mode, and to disable the provision of the plurality of feedback data bits to the LFSR while operating in the first mode.

11. An integrated circuit having built-in self-test (BIST) circuitry including a parallel data generator formed with a linear feedback shift register (LFSR) and multiple pluralities of serially coupled flip-flops, wherein the LFSR to concurrently output in parallel different data bits to different ones of the multiple pluralities of serially coupled flip-flops, and the multiple pluralities of serially coupled flip-flops concurrently feed back in parallel different data bits to different parts of the LFSR.

13. An integrated circuit having built-in self-test (BIST) circuitry including a multi-mode pseudo-random pattern generator (PRPG)/parallel decompressor to generate pseudo-random data vectors using a single LFSR while operating in a first mode, and to generate deterministic partially specified data vectors while operating in a second mode, with multiple portions of each of the deterministic partially specified data vectors being generated in parallel using the same single LFSR used to generate the pseudo-random data vectors of the first mode.

14. The integrated circuit as set forth in claim 13, wherein the integrated circuit further includes boundary scan registers.

15. An apparatus comprising a first and a second integrated circuit having a corresponding first and a second parallel data generator with the first parallel data generator providing either an output data bit from a linear feedback shift register (LFSR) of the first parallel data generator, or a copy of a feedback data bit to the LFSR of the first parallel data generator, as input to a LFSR of the second parallel data generator.

16. The apparatus as set forth in claim 15, wherein the first and second parallel data generators are correspondingly incorporated in first and second built-in self-test (BIST) circuitry of the first and second integrated circuits, and the first and second integrated circuits further including first and second boundary scan designs respectively.

17. An apparatus comprising a first and a second integrated circuit correspondingly having a first and a second dual purpose pseudo-random pattern generator (PRPG)/parallel decompressor with the first PRPG/parallel decompressor providing either an output data bit from a linear feedback shift register (LFSR) of the first PRPG/parallel decompressor, or a copy of a feedback data bit to the LFSR of the first PRPG/parallel decompressor, as input to a LFSR of the second PRPG/parallel decompressor.

18. The apparatus as set forth in claim 17, wherein the first and second PRPG/parallel decompressors are correspondingly incorporated in first and second built-in self-test (BIST) circuitry of the first and second integrated circuits, and the first and second integrated circuits further including first and second boundary scan designs respectively.

19. A method for loading a variable length data vector into a parallel decompressor comprising:

a) resetting a linear feedback shift register (LFSR); and

b) shifting a variable length data seed into the LFSR and then serially to a plurality of serially coupled flip-flop chains, overriding selected ones of data bits output from one flip-flop chain to another flip-flop chain.

20. The method as set forth in claim 19, wherein step (a) further comprises specifying the flip-flop chains by specifying a number of scan chains and their member flip-flops to be employed.

21. The method as set forth in claim 19, wherein step (b) further comprises configuring a plurality of multiplexors to select a first input to a linear feedback shift register (LFSR), and to select outputs of predecessor ones of the serially coupled flip-flop chains.

22. A method for decompressing a variable length data seed to concurrently generate in parallel multiple portions of a deterministic partially specified data vector, the method comprising:

a) configuring a linear feedback shift register (LFSR) to receive feedback data bits at selected positions of the LFSR as input;

b) configuring a plurality of scan chains to receive in parallel different output data bits from the LFSR;

c) enabling the scan chains to provide in parallel different feedback data bits to the plurality of selected positions of the LFSR; and

d) repeatedly applying clock cycles to shift the contents of the LFSR and the scan chains, until all flip-flops of the scan chains are filled with output data bits from the LFSR.

23. A method for applying a deterministic partially specified test pattern to an integrated circuit, the method comprising the steps of:

a) selecting a data seed corresponding to the deterministic partially specified test pattern;

b) conditionally reselecting scan chains of the integrated circuit and flip-flops of the scan chains, if a seed size of the data seed is dissimilar with an immediately preceding data seed;

c) loading the data seed into a linear feedback shift register (LFSR) and selected flip-flops of the selected scan chains;

d) decompressing the loaded data seed to generate in parallel multiple portions of the deterministic partially specified test pattern; and

e) applying the generated deterministic partially specified test pattern.

24. The method as set forth in claim 23, wherein the method further comprises step f) capturing test responses by the integrated circuit resulting from the application of the applied deterministic partially specified test pattern.

25. The method as set forth in claim 24, wherein the method further comprises steps g) repeating steps (a) through (f) for another deterministic partially specified test pattern, and h) repeating step (g) until all desired deterministic partially specified test patterns have been applied.

26. A method for applying a plurality of deterministic partially specified test patterns to a plurality of integrated circuits, the method comprising:

a) configuring the integrated circuits in a daisy-chained configuration with the integrated circuits sequentially outputting for each other;

b) selecting a group of data seeds corresponding to a subset of the plurality of deterministic partially specified test patterns;

c) conditionally selecting scan chains for each of the integrated circuits, and flip-flops of the selected scan chains, if seed sizes of the group of data seeds are correspondingly dissimilar with a prior group of data seeds;

d) loading the group of data seeds into a linear feedback shift register (LFSR) and specified flip-flops of selected scan chains of each of the plurality of integrated circuits;

e) decompressing the loaded group of data seeds to generate in parallel multiple portions of each of the subset of the deterministic partially specified test patterns; and

f) applying the generated subset of deterministic partially specified test patterns to the plurality of integrated circuits, when step (e) is completed for all integrated circuits.

27. The method as set forth in claim 26, wherein the method further comprises step g) capturing test responses by the plurality of integrated circuits resulting from the application of the generated subset of deterministic partially specified test patterns.

28. The method as set forth in claim 27, wherein the method further comprises steps h) repeating steps (a) through (g) for another subset of the deterministic partially specified test patterns, and i) repeating step (h) until the entire plurality of deterministic partially specified test patterns have been applied to the plurality of integrated circuits.

29. A storage medium having stored therein a first plurality of programming instructions to be executed by a computer system to insert built-in self-test (BIST) circuitry into an integrated circuit design, the BIST circuitry having a parallel decompressor to concurrently generate in parallel multiple portions of deterministic partially specified data vectors, wherein the parallel decompressor is formed with a LFSR and multiple flip-flop chains with the LFSR and the multiple flip-flop chains being structurally coupled to each other in a manner that allows a plurality of different data bits to be concurrently provided in parallel to different ones of the flip-flop chains and a plurality of different data bits to be concurrently feed back to different parts of the LFSR.

30. The storage medium as set forth in claim 29, wherein the storage medium further having stored therein a second plurality of programming instructions to be executed by the computer system for inserting a boundary scan design into the integrated circuit design.

31. The storage medium as set forth in claim 29, wherein the storage medium further having stored therein a second plurality of programming instructions to be executed by the computer system for generating data seeds for a plurality of deterministic test patterns to be used by the BIST circuitry to test the integrated circuit.

32. A computer system comprising:

a storage medium having stored therein a first plurality of programming instructions; and

an execution unit, coupled to the storage medium, to execute programming instructions stored in the storage medium including said first plurality of programming instructions which, when executed by said execution unit, insert a built-in self-test (BIST) circuitry into an integrated circuit design, the BIST circuitry having a parallel decompressor to concurrently generate in parallel multiple portions of deterministic partially specified data vectors from compressed data seeds, wherein the parallel decompressor being formed with a single LFSR and multiple flip-flop chains, with the LFSR and the multiple flip-flop chains being structurally coupled to each other in a manner that allows a plurality of different data bits to be concurrently provided in parallel to different ones of the flip-flop chains and a plurality of different data bits to be concurrently feed back to different parts of the LFSR.

33. The computer system as set forth in claim 32, wherein the storage medium further having stored therein a second plurality of programming instructions to be executed by the computer system for inserting a boundary scan design into the integrated circuit design.

34. The computer system as set forth in claim 32, wherein the storage medium further having stored therein a second plurality of programming instructions to be executed by the computer system for computing data seeds for a plurality of deterministic test patterns to be used by the BIST circuitry to test the integrated circuit.

35. A storage medium having stored therein an integrated circuit design including built-in self-test (BIST) circuitry having a parallel decompressor to concurrently generate in parallel multiple portions of a deterministic data vector, the parallel decompressor being formed with a single LFSR and multiple flip-flop chains with the LFSR and the multiple flip-flop chains being structurally coupled to each other in a manner that allows a plurality of different data bits to be concurrently provided in parallel to different ones of the flip-flop chains, and a plurality of different data bits to be concurrently feed back to different parts of the LFSR.

36. The storage medium as set forth in claim 35, wherein the integrated circuit design further includes boundary scan design.