Method of constructing stacked packages

• US 5,994,166 A
• Filed: 03/10/1997
• Issued: 11/30/1999
• Est. Priority Date: 03/10/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Brooks, Jerry M., Akram, Salman
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Zarneke, David A.
• Application Number:
  US08/813,467
• Time in Patent Office: 995 Days
• Field of Search: 438/108, 438/109, 438/455, 438/928, 438/FOR 368, 438/369, 257/686, 257/723, 257/778, 29/840
• US Class Current: 438/108
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1627 stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H05K 1/144 Stacked arrangements of planar printed circuit boards
• CPC Class Codes: Y10S 438/928 : Front and rear surface processing
• CPC Class Codes: Y10T 29/49144 : by metal fusion

Abstract

A semiconductor package comprising multiple stacked substrates having flip chips attached to the substrates with chip on board assembly techniques to achieve dense packaging. The substrates are preferably stacked atop one another by electric connections which are column-like structures. The electric connections achieve electric communication between the stacked substrates, must be of sufficient height to give clearance for the components mounted on the substrates, and should preferably be sufficiently strong enough to give support between the stacked substrates.

Claims

1. A method of fabricating a semiconductor assembly, comprising:

providing a base substrate of a planar non-conductive material having a first surface including a plurality of bond pads thereon and a second surface;

providing a first stacked substrate of a planar non-conductive material having a first surface and a second surface, said first surface and second surface of said first stacked substrate each includes a plurality of bond pads thereon;

disposing at least one first semiconductor die on said first surface of said first stacked substrate said at least one first semiconductor die including a plurality of bond pads;

disposing at least one second semiconductor die on said second surface of said first stacked substrate, said at least one second semiconductor die including a plurality of bond pads;

disposing at least one third semiconductor die on said first surface of said base substrate wherein said at least one third semiconductor die including a plurality of bond pads;

coupling at least one first intercoupler electrically between at least one of said plurality of first surface bond pads of said first stacked substrate and at least one of said plurality of said bond pads on said second surface of said first stacked substrate, and at least one of said plurality of bond pads of said first semiconductor die;

coupling said at least one first intercoupler electrically between at least one of said plurality of said bond pads of said first surface of said first stacked substrate and at least one of said plurality of bond pads on said second surface of said first stacked substrate, and at least one of said plurality of second semiconductor die bond pads;

providing at least one second intercoupler extending between and electrically coupling said base substrate and said first stacked substrate, said second intercoupler physically positioning said first stacked substrate in a substantially parallel spaced relationship to said base substrate;

providing a second stacked substrate of a planar non-conductive material having a first surface and a second surface, the first surface and the second surface of said second stacked substrate each including a plurality of bond pads;

disposing at least one fourth semiconductor die on said first surface of said second stacked substrate, said fourth semiconductor die including a plurality of bond pads;

p1 disposing at least one fifth semiconductor die on said second surface of said second stacked substrate, said fifth semiconductor die includes a plurality of bond pads,

electrically coupling at least one third intercoupler between at least one of the plurality of bond pads on the first surface of said base substrate and said third semiconductor die;

electrically coupling at least one fourth intercoupler between at least one of said plurality of bond pads on said first surface of said second stacked substrate and bond pads on said second surface of said second stacked substrate and at least one of said plurality of fourth semiconductor die bond pads;

electrically coupling at least one fifth intercoupler extending between and electrically coupling said second stacked substrate and one of said first surface of said first stacked substrate, said second surface of said first stacked substrate, and said first surface of said base substrate, said fifth intercoupler separating said second stacked substrate from at least one of said first surface of said first stacked substrate, said second surface of said first stacked substrate, and said first surface of said base substrate;

disposing a dielectric material between said first surface of said first stacked substrate and said bond pads on said first semiconductor die;

disposing a dielectric material between said first surface of said base substrate and said second surface of said first stacked substrate; and

encapsulating said first stacked substrate, said second stacked substrate, said at least one first semiconductor die, at least one second semiconductor die, said at least one third semiconductor die, said at least one fourth semiconductor die, said at least one fifth semiconductor die, and the upper surface including a plurality of bond pads thereon of said base substrate in an encapsulation material.

2. The method of claim 1, wherein providing said at least one second intercoupler includes disposing said at least one second intercoupler intermediate at least one of said plurality of bond pads on said first surface and first stacked substrate second bond pads on said second surface of said first stacked substrate, and at least one of said plurality of bond pads on said first surface of said base substrate.

3. The method of claim 1, wherein said at least one first intercoupler includes at least one of the group consisting of solder, conductive adhesives, Z-axis conductive material, flex-contacts, spring contacts, wire bonds, and TAB tape.

4. The method of claim 3, further comprising attaching electrical connection means to said plurality of bond pads on said second surface of said base substrate for electrical communication with external circuitry.

5. The method of claim 4, further comprising providing a plurality of trace leads on said base substrate for electrical communication between said plurality of bond pads on said first surface of said base substrate and said plurality of bond pads on said second surface of said base substrate.

6. A method of fabricating a semiconductor assembly, said method comprising the steps of:

forming a base substrate of a planar non-conductive material having a first surface including a plurality of bond pads thereon;

forming a first stacked substrate of a planar non-conductive material having a first surface including a plurality of bond pads thereon and a second surface including a plurality of bond pads thereon;

forming a second stacked substrate of a planar non-conductive material having a first surface including a plurality of bond pads thereon and a second surface;

disposing at least one semiconductor die on said first surface of said first stacked substrate;

disposing at least one semiconductor die on said second surface of said first stacked substrate;

disposing at least one semiconductor die on said first surface of said second stacked substrate;

disposing at least one semiconductor die on said second surface of said second stacked substrate;

forming at least one base substrate trace lead connected to at least one bond pad of said plurality of bond pads on said first surface of said base substrate;

forming at least one first stacked substrate trace lead connected to at least one bond pad of said plurality of bond pads on said first surface of said first stacked substrate and at least one bond pad of said plurality of bond pads on said second surface of said first stacked substrate;

forming at least one second stacked substrate trace lead connected to at least one bond pad of said plurality of bond pads on said first surface of said second stacked substrate;

connecting said at least one semiconductor die on said first surface of said first stacked substrate to said at least one first stacked substrate trace lead;

connecting said at least one semiconductor die on said second surface of said first stacked substrate to said at least one first stacked substrate trace lead;

connecting said at least one semiconductor die on said first surface of said second stacked substrate to said at least one second stacked substrate trace lead;

connecting at least one bond pad of said plurality of bond pads on said first surface of said second stacked substrate to at least one bond pad of said plurality of bond pads on said second surface of said first stacked substrate;

connecting at least one bond pad of said plurality of bond pads on said first surface of said first stacked substrate to at least one bond pad of said plurality of bond pads on said first surface of said base substrate;

forming a plurality of bond pads on the second surface of said second stacked substrate,

forming a third stacked substrate of a planar non-conductive material having a first surface including a plurality of bond pads thereon and a second surface;

disposing at least one semiconductor die on said first surface of said third stacked substrate;

forming at least one third stacked substrate trace lead connected to at least one bond pad of said plurality of bond pads on said first surface of said third stacked substrate;

connecting said at least one semiconductor die on said first surface of said third stacked substrate to said at least one third stacked substrate trace lead;

connecting at least one bond pad of said plurality of bond pads on said second surface of said second stacked substrate to at least one bond pad of said plurality of bond pads on said first surface of said third stacked substrate; and

encapsulating said base substrate, said first stacked substrate, said second stacked substrate, and said third stacked substrate in an encapsulation material.