×

Compensation of the channel region critical dimension, after polycide gate, lightly doped source and drain oxidation procedure

  • US 5,994,192 A
  • Filed: 05/29/1998
  • Issued: 11/30/1999
  • Est. Priority Date: 05/29/1998
  • Status: Expired due to Term
First Claim
Patent Images

1. A method for fabricating a MOSFET device, on a semiconductor substrate, comprising the steps of:

  • forming a gate insulator layer on said semiconductor substrate;

    depositing a polysilicon layer;

    depositing a metal silicide layer;

    depositing a composite insulator layer;

    forming a photoresist shape;

    anisotropic etching of said composite insulator layer, using said photoresist shape as an etch mask, creating a straight walled composite insulator shape, with the width of said straight walled composite insulator shape equal to the width of said photoresist shape;

    forming a polycide gate structure comprised of a metal silicide shape, on a polysilicon shape, via isotropic etching of said metal silicide layer, creating said metal silicide shape, with the width of said metal silicide shape narrower than the width of said photoresist shape, and via an anisotropic etching of said polysilicon layer, using said photoresist shape as a mask, creating a straight walled polysilicon shape, with the width of said straight walled polysilicon shape equal to the width of said photoresist shape;

    growing a first oxide layer on the exposed sides of said metal silicide shape;

    growing a second oxide layer on the exposed sides of said straight walled polysilicon shape;

    ion implanting a first conductivity imparting dopant into a region of said semiconductor substrate, defined by said second oxide layer, on the sides of said straight walled polysilicon shape, to form a lightly doped source and drain region;

    forming insulator spacers on the sides of said composite insulator shape, and on the sides of said polycide gate structure; and

    ion implanting a second conductivity imparting dopant into a region of said semiconductor substrate, defined by said insulator spacers, on the sides of said polycide gate structure, to form a heavily doped source and drain region.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×